Yield and Variability Optimization of Integrated Circuits

243 Pages·1995·14.92 MB·English

by  J. C. Zhang, M. A. Styblinski (auth.)

YIELD AND VARIABILITY
OPTIMIZATION OF
INTEGRATED CIRCUITS
YIELD AND VA RIABILITY
OPTIMIZATION OF
INTEGRATED CmCUITS
J.C. Zhang
Westem Atlas International Ine.
M.A. Styblinski
Texas A & M University
Springer Science+ Business Media, LLC
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available from
the Library of Congress.
Copyright c 1995 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1995
Softcover reprint of the hardcover Ist edition 1995
Ali rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanica1,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+BusinessMedia,LLC
Printed on acid-free pap er.
ISBN 978-1-4613-5935-7 ISBN 978-1-4615-2225-6 (eBook)
DOI 10.1007/978-1-4615-2225-6
CONTENTS
LIST OF FIGURES ix
PREFACE
Xlll
1 INTRODUCTION 1
1.1 Design for Quality and Manufacturability 1
1.2 Notation 2
1.3 Interpretation ofBasic Concepts 4
1.3.1 Parametric Yield Optimization 7
1.3.2On-Target Design 8
1.3.3Variability Minimization 10
1.3.4Worst-Case Measure Reduction 15
1.4 Summary 16
2 OVERVIEW OF IC STATISTICAL MODELING 17
2.1 Introduction 17
2.2 Process Variations 19
2.2.1 Process-Oriented Approach 19
2.2.2Device-Oriented Approach 24
2.2.3Inter-Die Variations 25
2.2.4Intra-Die Variations 28
2.3 Environmental Variations 30
2.4 Statistical Macromodeling 31
2.5 Summary 31
3 DESIGN OF EXPERIMENTS 33
3.1 Introduction 33
v
VI YIELD AND VARIABILITY OPTIMIZATION
3.2 Experiment Analysis 34
3.3 Orthogonal Arrays 37
3.4 Main Effect Analysis 39
3.5 Interaction Analysis 46
3.6 Taguchi Experiments 48
3.6.1 Taguchi's Parameter Design Experiment 48
3.6.2 Mathematical Model Behind the Taguchi Experiments 48
3.7 Summary 52
4 PARAMETRIC YIELD MAXIMIZATION 55
4.1 Introduction 55
4.2 Yield Estimation 58
4.2.1 Monte Carlo (MC) Method 58
4.2.2Importance Sampling 60
4.2.3 Function Approximation 63
4.2.4Other Yield Estimation Methods 65
4.3 Indirect Yield Improvement 68
4.3.1 SimplicialApproximation 69
4.3.2Worst-Case Distance-Driven Design Centering 73
4.3.3Performance Space-Oriented Design Centering 73
4.4 Direct Yield Optimization Methods 77
4.4.1 Methods Using Standard DeterministicOptimizationAl-
gorithms 77
4.4.2Large-Sample Methods 79
4.4.3Small-SampleStochastic Approximation Methods 83
4.5 Generalized and Orthogonal Array-Based Gradient Methods
for Discrete Circuits 86
4.5.1 Generalized p.dJ. 87
4.5.2Generalized Yield Gradient 88
4.5.3MC based Yield Gradient Estimation 90
4.5.4OA based Yield Gradient Estimation 91
4.5.5 Empirical Tests ofthe OA Design Approach 95
4.6 Gradient Methods for Integrated Circuits 102
4.6.1The Perturbation Method 102
4.6.20A Design-Based Ie Yield Gradient Estimation 104
4.7 Examples 106
Contents VB
4.7.1 Example 1: CMOS Delay Circuit 106
4.7.2 Example 2: CMOS Clock Driver 114
4.7.3 Example 3: CMOS OTA 120
4.8 Summary 123
5 VARIABILITY MINIMIZATION AND TUNING 125
5.1 Introduction 125
5.2 Principles ofDiscrete Circuit Variability Minimization 127
5.3 Principles ofIC Variability Minimization 131
5.4 Factor Screening 136
5.4.1 Identification ofCritical Noise Factors 137
5.4.2Identification ofCritical Designable Factors 138
5.4.3Example 1 138
5.5 Taguchi's on-target Design 141
5.5.1 On-Target Design 141
5.5.2Example 2 142
5.6 Two-Stage Design Strategy 142
5.6.1 Dynamic Screening with Variability Minimization 143
5.6.2 Example 3 144
5.6.3Performance Tuning 144
5.6.4Algorithm Description 146
5.7 Example 4: CMOS Delay Circuit 147
5.8 Example 5: CMOS Clock Driver 153
5.9 Summary 157
6 WORST-CASE MEASURE REDUCTION 161
6.1 Introduction 161
6.2 The ±O'Transistor Modeling 163
6.3 Worst-Case Measure Minimization 167
6.3.1 Statistical Interpretation 167
6.3.2 Example 1 170
6.4 Commentson the ±O' Model 175
6.5 Creation ofWorst-Case Models From the Statistical Model 177
6.5.1 Methodology 177
6.5.2Example 2 178
6.6 Summary 183
Vlll YIELD AND VARIABILITY OPTIMIZATION
7 MULTI-OBJECTIVE CIRCUIT
OPTIMIZATION 185
7.1 Introduction 185
7.2 Multiple-Objective Optimization: An Overview 186
7.2.1 Pareto Critical Points 186
7.2.2Weighted-Sum Minimization 187
7.2.3Minimax Approach 187
7.3 Fuzzy Sets 189
7.3.1 Membership Functions 189
7.3.2Intersection Operation 192
7.4 Multiple-Performance Statistical Optimization 194
7.4.1 Fuzzy Quality Index 195
7.4.2Statistical Quality Measures 195
7.4.3Yield Maximization 197
7.4.4 "On-Target" Design 199
7.4.5Example 1 202
7.5 Multiple-Performance Variability Minimization 205
7.5.1 Fuzzy Variability and Bias Measures 205
7.5.2 Example 2 208
7.6 Summary 209
A COMMONLY USED ORTHOGONAL ARRAYS 211
A.l Level 2 Orthogonal Arrays 211
A.2 Level 3 Orthogonal Arrays 213
B SPICE3 INPUT DECKS 215
B.l CMOS Delay Circuit 215
B.2 CMOS Clock Driver 218
REFERENCES 221
INDEX
233
LIST OF FIGURES
Chapter 1
1.1 (a) Voltage divider, (b) Its acceptability region 5
1.2 Dependence ofyield on nominal design 6
1.3 Region ofdesigns with 100 %yield 9
1.4 Comparison of£ with ¢ 10
1.5 Two low yield situations 11
1.6 Dependence ofvariability on nominal design 13
1.7 Histogramsofy for the voltagedivider before and after variabil-
ity minimization 14
Chapter 2
2.1 Process-oriented nominal IC simulation 20
2.2 Hierarchical statistical generation of process disturbances 21
2.3 Statisticalsimulationscheme for the process levelstatistical design 23
2.4 Statistical simulation scheme for the circuit level statistical IC
design 24
2.5 Propagation ofprocess disturbances to device model parameters 25
2.6 An NMOS voltage divider and its VTH correlation 26
Chapter 3
3.1 Geometrical interpretation of£9(34) in 3-D space 39
3.2 An exampleofthe Taguchi experimental design 49
Chapter 4
4.1 An outer approximation to the acceptability region 61
4.2 Radial exploration approach to yield estimation 66
4.3 Interpretation of "local yield" calculation along a parallel. 68
IX
x YIELD AND VARIABILITY OPTIMIZATION
4.4 Simplicial Approximation approach to design centering 71
4.5 Design centering for IC yield optimization 72
4.6 Yield improvement by the center-of-gravity method 80
4.7 Interpretation ofyield gradient for uniform p.d.f 92
4.8 Two different sampling strategies 93
4.9 Example 1: A CMOS delay circuit 107
4.10 Example 1: Nominal response ofthe initial design 108
4.11 Example 1: SPICE3 simulationscheme 110
4.12 Example 1 : Delay distributions 113
4.13 Example 2 : A CMOS clock driver circuit 115
4.14 Example 2 : Nominal response ofinitial design 116
4.15 Example 2 : Clock skew distributions 119
4.16 Example 3 : CMOS OTA 122
Chapter 5
5.1 Illustration ofsensitivity minimization for discrete circuits 131
5.2 Distributions ofdelay 149
5.3 Behavior ofuy,ii, uy/ii and EQL between xO and x; 151
5.4 Behavior ofuy,ii, uy/ii and EQL along XO -+ xj -+ x; 152
5.5 Clock driver: skew distributions 156
5.6 Clock Driver: yield vs. specifications 159
Chapter 6
6.1 Illustration ofI-V Curve Variations 165
6.2 Statistical Variation of1-V Curves 166
6.3 The worst-case transient responses before optimization 173
6.4 The worst-case transient responses after optimization 174
Chapter 7
7.1 A possible membership function ofa fuzzy set 190
7.2 A class ofmembership functions 191
7.3 Illustration offuzzy set intersection 192
7.4 Illustration ofthe fuzzy quality index 196
7.5 Membership functions for yield maximization 198
List of Figures
Xl
7.6 A membership function for on-target design for different values
ofq= 2,4,6 200
7.7 A membershipfunction for thesmaller-the-better case for differ-
ent values ofq= 2,4,6 201
7.8 Illustration offuzzification and intersection operations ofstatis-
tical measures 206
7.9 A membership function for variability fuzzification for different
values of(1i 207
Appendix A
Appendix B