Table Of ContentLecture Notes ni
Computer Science
Edited yb .G Goos dna .J Hartmanis
253
I I I
J.D. Becker .i Eisele (Eds.)
WOPPLOT 86
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Springer-Verlag
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Editorial Board
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Editors
J6rg D. Becker
tgnaz Eisele
tnstitut fLir Physik, Fakuit&t fiJr Etektrotechnik
Universit~.t der Bundeswehr MSnchen
Werner-Heisenberg-Weg 39, D-8014 Neubiberg, FRG
CR Subject Classification (1987): B.7.1, C.1.2, C,1.3, Et,3, E4,1, 1.2.3, J.2.
ISBN 3-540-18022-2 Springer-Verlag Berlin Heidelberg New York
ISBN 0-387-18022-2 Springer-Verlag New York Berlin Heidelberg
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ECAFERP
erehW" else can you listen to a philosopher dna a cyberneticist discussing the
nature of time?" exclaimed enthusiastically eno of the participants to TOLPPOW 86.
His reaction characterizes best the spirit of the workshop. Three years after
TOLPPOW 38 (which saw published as Vol. 691 of Springer Lecture Notes in Physics) ew
decided to hold another workshop. ruO aim saw to collect emos current work as well
sa some future perspectives of parallel processing in order to get emos feeling
for the necessary technological developments.
Silicon technology, in particular in connection with molecular maeb epitaxy, could
provide for more local memory dna more connections in the course of the next years,
even if many problems have still to eb solved. A possible competitor is molecular
electronics; but with structures in silicon getting smaller dna smaller it might
eb difficult for molecular electronics to catch up.
enO of the basic questions of parallel processing is that of the organizational
structure, which - pu to won - is more dictated by technology than by needs. -woH
ever, since the invention of structured design dna object-oriented programming it
sah emoceb clear that there ought to eb na intimate relationship between problem
structure, logical structure, dna organizational structure.
A structure that occurs frequently is hierarchical organization ("pyramid architec-
ture"). It is also the only eno for which a closed, consistent theory exists, at
least in the case of equilibrium.
saerehW the state of the art concerning machines SlMD is quite satisfactory, a
general concept for DMIM machines is still missing. That such machines should
exist is suggested at least by considering the brain. Mental representations are
therefore of interest also for parallel processing. Furthermore, the above-mentioned
connection between structure dna logics yam suggest that ew cannot expect DMIM
machines to work in the framework of Boolean logics.
In spite of many open questions (including that of parallelizability) parallel
computation is already being applied to many practical problems, mainly in
physics dna in image processing.
VI
emoS of the papers have been modified after the workshop. For this dna also for
emos technical reasons there sah been emos delay in the publishing of the pro-
ceedings. eW should like to thank the editors of SCNL dna the Springer-Verlag for
their patience dna cooperation.
eW gratefully acknowledge financial support from our sponsors:
Siemens ,GA nehcnUM
Freundeskreis der Universit~t der Bundeswehr ,nehcnUM Neubiberg
Neubiberg~ yaM 7891 J. Becker I. Eisele
STNETNOC
I. Eisele
Technological Developments for Three-Dimensional Circuitry ................... I
.M Mehring, H. Sixl
Molecular Electronics: Storage and Transport ................................. 11
oH Ritter, K. Schulten
Planning a Dynamic Trajectory via Path Finding in Discretized Phase Space .... 92
.G Fritsch
Numerical Simulation of Physical anemonehP by Parallel Computing ............. 40
V. Cantoni, .M Ferretti
Pyramidal Architectures for Image Processing ................................. 58
P. Weidner
DMIM Algorithms and Their Implementation ..................................... 57
.G Scarpetta, .G Simoncelli
Self-Organizing Hierarchical Modular Systems ................................. 78
P. Molzberger
Analyzing Mental Representation by Means of PLN (Neuro Linguistic Programming) 021
.G Brewka
Nonmonotonic Reasoning: Formalizations and Implementations ................... 631
A. v. MUller
Towards a Complex Notion of Time ............................................ 051
J. .D Becker
Structure and Parallel Processing ........................................... 851
U. RUckert, K. Gonser
Adaptive Associate Systems for VLSI ......................................... 661
.M .R B. Forshaw
Pattern Storage and Associative Memory in Quasi-Neural Networks ............. 581
lV
E.R. Caianiello, .M Marinaro
Neural Nets and Cellular Automata ........................................... 891
A. Bertoni, .M Goldwurm, .G Mauri, .N Sabadini
Parallel Algorithms and the Classification of Problems ...................... 602
LACIGOLONHCET STNEMPOLEVED ROF LANOISNEMID-EER4~ YRTIUCRIC
I. Eisele
Fakult~t fur Elektrotechnik, Institut fur Physik
Universit~t der Bundeswehr ,nehcnUM D-8014 Neubiberg
NOITCUDORTNI
Within the scope of the serial nov nnamueN type computer architecture the develop-
ment in the past saw mainly directed towards larger information capacity dna a fas-
ter sequential flow of operations. However, to solve problems such as image proces-
sing or other associative processes~parallel computer configurations are hcum better
suited. Favoured by the rapid technological progress in the production of very large
scale integrated (VLSI) circuits presently it sah emoceb economically feasible to
construct parallel processing systems by interconnecting hundreds or even thousands
of processors dna yromem modules.
Examples are processing units with a two dimensional array of boolean processors,
each of which is connected to several neighbours, or pipeline architectures in which
a stream of data enters the system, is processed by the first stage, the output from
which is processed by the second stage, dna so on. Furthermore the data transfer in
a distributed system nac eb provided by a complex sub structure.
In every case the system is constructed from chips which in turn have a serial data
flow. Therefore it is necessary to discuss restrictions dna possible wen develop-
ments of integrated circuits with respect to parallel architecture.
SNOITCIRTSER FO ROTCUDNOCIMES YGOLONHCET
Before discussing possible ways to achieve higher complexity of electronic systems
it is necessary to know emos of the restrictions of present day technology. emoS of
these limits are eud to the concept of planar technology but emos of them are more
general dna arise from the electronic transport in solids. In the following emos of
the critical limits are summarized.
Planar technology
In the conventional technology the substrate always consists of single crystalline
semiconductor materials because for any other material selection neither reproduci-
bility nor degradation nac eb controlled sufficiently for the mass production of
highly complex circuits. ehT overall properties of the semiconductors nac eb modi-
fied by doping methods such sa diffusion, ion implantation, dna epitaxy. In combi-
nation with photolithography dna masking layers local doping concentrations nac eb
achieved.
sA a result only regions near the substrate surface nac eb accessed. Typical dimen-
sions for na enhanced SOMC (Complementary Metal-Oxide-Semiconductor) process are
given in Fig. 1. Whereas the lateral dimension of na active device amounts, to about
1 mp for the effective channel length Leff,the vertical dimensions exceed this value
by far.
p-CHANNEL ~ n-CHANNEL T.
\ +.. i +, f'---
DLEIF EDIXO r~,:,,;'l i ~ i ~ ......... I I::
=,n iiX 1 mil <£~ ~"~ ~
LLEW_-n .~ I' N.~ S.N
n- - EPILAYER
+ - n SUBSTRATE
Fig. 1 Typical dimensions for a Complementary Metal-Oxide Semiconductor
)SOMC( process.
ehT growth of additional layers is restricted to 3 or 4 metallization levels which
nac eb used for connections. However, the existence of amorphous insulators dna
poly-crystalline metals excludes the growth of another layer of single crystalline
semiconductor material for active devices. sA a result the arrangement of devices
must eb two-dimensional.
Having in mind the technological restrictions of planar technology eno nac won -moc
pare the dimensionality of na ideal circuit with a real system (see Table 1). For
the chip it can eb seen that the spatial extension of devices (3-D) dna connections
(2-3 )D sah a high dimensionality dna therefore their arrangement no a substrate sah
a low dimensionality. Especially the limited number of connections explains yhw it
is useful to replace spatial connections by time steps, i.e. esu of serial instead
of parallel data processing for a computer.
Even if more than eno layer with active elements could eb fabricated with planar
technology, the complex masking procedures would probably prohibit production of
such devices. Each masking step consists of many individual steps such as cleaning,
photolithography, etching, dna os on. ehT total yield y of a process nac eb crudely
decribed by Bose-Einstein statistics:
y = 1 )1(
(i + ADo n)
where n is the number of masking steps, A the area of the chip, dna o O the average
defect density. This means that the yield decreases with increasing chip area sa
well as masking steps. For a three dimensional array of devices this means that the
ideal dim. real dim.
C Active device 3
H Arrangement of devices 2
I Connections 2-3
P Arrangement of connections + i
S Arrangement of chip.s 2-3
Y
S
T Arrangement of connections 1-2
E
M
I
Table 1 Dimensionality of Semiconductor Circuits dna Systems
complexity of each masking step sah to eb reduced significantly.
Thermal limit
Besides the geometrical dimensions dna the arrangement of active devices as well sa
connections which are typical for planar technology there exist other more general
limits eud to the electronic transport behaviour in solids. For electronic circuits
the information per bit is carried by some 01 5 electrons dna according to their re-
combination behaviour a power loss occurs which sah to eb dissipated within the -am
terial dna removed in order to avoid heating . ehT powerloss P for a potential drop
VA is given by
P = Pstatic + Pdynamic
VAV fR L C
P = n T L ( ~ + I ~ ) ~ ~ I~V + CV~Vfn (2)
where n is the number of active elements, f the clocking frequency. ehT voltage V
dna the technologically realized capacity C determine the charge Q which is neces-
sary for the information storage of eno bit.
Because the mumixam allowable power loss P is given by the thermal resistance bet-
neew the chip dna the outside world P( ~ mcW1 "2 without additional cooling) eno ob-
tains:
nf = constant (3)
It snaem that the product between the number of active devices dna the clocking fre-
quency is a constant which still depends no technology. This is a thermal restric-
tion which holds independently of the geometrical arrangement of devices. For a
three dimensional circuitry with a significant increase in total number of devices
this might have the consequence of a reduced clocking frequency.
Connection Limit ! s ~ speed)
The speed of a signal along a signal line is determined by rise times t r and delay
times t d which are connected to the charging and discharging of capacitances. The
ideal delay time is given by [1]:
tmi n
d = 0.89 CcR c (4)
c where c and R C are resistance and capacitance of the interconnection. ehT output
resistance o R of the loading transistor has also to eb taken into account and yields
[2]:
¥2~ [ RcC c 2
tr = cCoR( +--2--- ) - ]cCcL
(5)
t r ~ 2.5 CoR c + 1.25 CcR c
For a i mc long aluminum interconnection with a sheet resistance of 0.1 ~/D and
2 as SiO the dielectric the RC-limited propagation delay is about 2 • 10-10[S] (see
Fig. 2).
s o2/si
Z
0
SAPPHIRE
0 lcm AI (0.1~/u)
t
0.01
01 001
W [#m] =-
Fig. 2 Propagation delay of 1A interconnects on Si02/Si and Saphire.
This will be the limiting speed for a circuit with a complex wiring as it is neces-
sary for parallel processing.
