Table Of ContentQualcomm Technologies, Inc.
WCD9335 Audio Codec
Device Specification (Advance Information)
80-NT781-1 Rev. E
September 15, 2015
Confidential and Proprietary – Qualcomm Technologies, Inc.
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WCD9335 Audio Codec Device Specification (Advance Information)
Device description Summary of key features
The WCD9335 is a standalone Hi-Fi audio codec IC that supports The industry’s first 40 nm codec – lower cost, smaller footprint
Qualcomm Technologies, Inc. (QTI) multimedia solutions, including while enabling high-percentage digital content
the MSM8996, MSM8976, and MSM8956 chipsets. Key WCD9335 Ultra low-power voice activation engine for keyword detection
functions include: and user identification
SLIMbus for access to all on-chip digital audio channels; I2S Low-power, high-performance ultrasound support, including
accesses fewer paths, but maintains compatibility with earlier analog MIC and line output
modem ICs
Hi-Fi audio recording and playback – 110 dB ADC and 130 dB
Soundwire interface for driving WSA8810 or WSA8815 speaker DAC SNR
amplifiers
32bit/384 kHz, 44.1 kHz native processing
Six analog input ports and seven analog output ports
Supports external smart speaker amplifiers such as
Six audio analog-to-digital converters (ADCs) and seven WSA8810/WSA8815 with two-wire Soundwire signaling to
digital-to-analog converters (DACs) provide configuration flexibility and reduce PCB design
Six digital microphone inputs (three clock/data pairs) complexity
Multi-button headset control (MBHC) for smart accessory Class-H headphone amplifier – 123 dB dynamic range and
detection -105dB THD+N
Digital processing includes MBHC, including an additional pin to support both tip and
Microphone activity detection (MAD) detecting audio, ground insertion/removal
ultrasound, and beacon activity Ground reference pin for line outputs to improve signal integrity
for docking stations
Ultrasonic proximity and pen detection and tone generator
Only two external supplies required; all other needed voltages
Qualcomm® Snapdragon™ Voice Activation subsystem
are generated by WCD9335 support circuits
Active noise cancellation (ANC) Highly integrated 4.17 × 3.91 mm FOWPSP package
Integrated analog support reduces BOM and area Low-power 40 nm CMOS fabrication technology
Microphone bias outputs (x4) See Section1.2 for a complete list of WCD9335 features.
SIDO buck and SIMO flyback circuits
Refer to 80-NT781-5 for complete functional & interface details.
WCD9335 high-level block diagram and package type
4.17
WCD9335
Digital Interfacerouter
DMICI/F processing ®isters QUALCOMM
x6
(x3) WCD9335
MICmultiplexing
Host
MBHC Decimators Hostdigital IC 3.91
Batterymonitor
interfaces
Ultrasonic
proximityandpen
x6 ADC detection SLIMbusRx/Tx
I2SRx
Analogaudio
WSA8810/ Gains&mixing I2STx
WSA8815 inputs(x6) Snapdragon I2Cslave (0.65MAX)
speakeramps VoiceActivation DiscreteI/Os 113 FOWPSP
SoundwireI/F Activenoise 45º
cancellation
Analogaudio
Interpolators Supportcircuits
outputs(x7)
IIRfilters
BuckSIDO
x7 DAC Dynamicrange
BuckSMPS
enhancement
Earpiece SIMOFlyback (0.35)
Class-Hcontrol
Stereo Ultrasonic LDOs
headphones proximitytone MICbias(x4)
Lineoutputs generator BandgapVref
SmartBoost JTAG Download the 113 FOWPSP
outline drawing: NT90-NT388-1
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WCD9335 Audio Codec Device Specification (Advance Information)
Supply voltage summary
Two supplies are required:
Primary phone power (VPH_PWR)
Regulated 1.8 V from power management
On-chip circuits generate all other voltages needed by the WCD9335.
Revision history
Revision Date Description
A December 2014 Initial release
B February 2015 Updated device description, key features and high-level block diagram, and
package type
Section1.1 WCD9335 detailed functional block diagram: Updated the block
diagram
Section1.3 Features: Made multiple changes to the table
Table2-3 Pin descriptions – analog outputs: Updated the functional description
for LINE_OUT_REF
Globally replaced SIDO SMPS with SIDO buck
Table2-6 Pin descriptions – support circuits: Updated flyback SIMO voltage
converter to SIMO flyback and made multiple edits to that section
Table2-8 Pin descriptions – power supply pins: Updated the functional
descriptions for PA_VNEG and PA_VPOS
Added content to the following chapters:
Chapter3 Electrical Specifications
Chapter4 Device Marking & Ordering Information: Added the package
outline drawing
Chapter8 Device and Documentation Support: Updated the definitions for
SIDO and SIMO
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WCD9335 Audio Codec Device Specification (Advance Information)
Revision Date Description
C March 2015 Changed the document title to datasheet (from device specification) throughout
the document
Added the supported chipsets
Section1.3 Features:
Updated Snapdragon Voice Activation power number at battery with 100%
speech occupancy
Updated the sampling rate supported on the Tx SLIMbus port
Updated the supported digital microphone output clock frequency
Added an integrated IEC ESD diode feature on differential ear outputs,
stereo headphone, and HPH_REF pins
Chapter2 Pin definitions: Changed pin 113 to DNC in the pin map and pin
tables
Table3-10 Serial interface through mono EAR output: Updated output power
test conditions for 32 Ω load
Table3-12 Serial interface through stereo-differential line outputs: Updated
output load conditions
Table3-13 Serial interface through stereo LINE output: Updated output load
conditions
Section3.6.3 Digital serial interface through stereo Hi-Fi differential line
outputs: Added “stereo” to the section title and introduction
Section3.7 Digital I/Os and digital processing: Clarified WCD9335 content and
corrected
Table3-21 Supported I2C standards and exceptions: Corrected the I2C
specification reference
Chapter4 Device marking and ordering information: Corrected the package
outline drawing and removed excess links
Chapter8 Device and Documentation Support: Added the DCN for the daisy
chain and land stencil drawings
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WCD9335 Audio Codec Device Specification (Advance Information)
Revision Date Description
D June 2015 Changed the document title to device specification (from datasheet) throughout
the document
Section1.3 Features:
Updated CPE on-chip RAM memory to 304 KB
Updated HPH CnP to 10 μVpp
Clarified LDOH output voltage is fixed to 3 V
Chapter3 Electrical specifications:
Changed parameter IMD2 to IMD
Corrected or clarified test conditions:
– Table3-4 Power consumption for typical use cases: Updated power
consumption for typical use cases
– Table3-7 Analog input through digital serial interface performance:
Updated Tx analog input CMRR parameter and end-to-end frequency
response
– Table3.8 Tx digital decimation filter performance (all supported
sampling rates): Updated Tx decimation filter frequency response
– Table3-9 Digital microphone input through digital serial interface
performance: Updated DMIC frequency response parameter
– Table3-11 Serial interface through HPH output: Updated HPH
48 kHz/44.1 kH/16-bits and 384 kHz/32-bits performances to target
specifications, minimum supported load, disabled output impedance,
and frequency response parameters
– Table3-11 Serial interface through stereo-differential line outputs:
Updated differential line output test setup, disabled output impedance,
turn on/off click, and frequency response parameters
– Table3.14 Rx digital interpolation filter performance (all supported
sampling rates): Replaced transition band attenuation with frequency
roll-off under test conditions for 96 kHz and 192 kHz
Updated with ES silicon data: Table3-7 Analog input through digital serial
interface performance, Table3-10 Serial interface through mono EAR
output, Table3-13 Serial interface through stereo LINE output, and
Table3-24 Microphone bias performance
Table3-24 Microphone bias performance: Added test setup note for
microphone bias
Table3.25 MBHC impedance detection: Added impedance detection click-
and-pop data
Chapter4 Device marking and ordering information: Added Section4.1 Part
marking, Section4.2 Device ordering information, Section4.3 Device moisture-
sensitivity level, and Section4.4 Thermal characteristics
Chapter5 Carrier, storage, & handling information: Updated entire chapter
Chapter6 PCB mounting guidelines: Updated entire chapter
Section7.2 Qualification sample description: Updated fab sites and assembly
sites
Section8.3 Terms and acronyms: Added FOWLP acronym and correct
definition for WCD
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WCD9335 Audio Codec Device Specification (Advance Information)
Revision Date Description
E September 2015 Section1 Introduction:
Global change: Replaced all references of “WSA PDM interface” with
“Soundwire interface”
New features for 2.0 version hardware:
– Moisture detection
Section3 Electrical specifications
Updated electrical specifications for 1.1 version hardware
Table3-1 Absolute maximum ratings: Updated maximum operating voltage
on VDD_MIC_BIAS and VBAT_ADC_IN pins
Table3-2 Operating conditions: Updated maximum operating condition
voltage for the VDD_MIC_BIAS and VBAT_ADC_IN pins
Table3-4 Power consumption for typical use cases: Updated typical power
consumption for different audio use-cases
Table3-6 Analog input through digital serial interface performance:
Removed power consumption; specification is already in Table 3-4
Table3-10 Serial interface through HPH output: Updated HPH frequency
response specification
Table3-11 Serial interface through stereo-differential line outputs: Updated
stereo Hi-Fi differential line outputs specification
Table3-12 Serial interface through stereo LINE output: Added IMD
specifications for narrow-band and wide-band voice call use-case
Section4 Device marking and ordering information:
Figure4-3 Device identification code and Table4-2 Device identification
code/ordering information details: Updated device identification code for
WCD9335 2.0 HW ES2
Figure5-1Carrier tape drawing with part orientation:
Updated units per reel for ES2 hardware
Section8.2 Support documentation:
Updated thermal package model document number
Added document number for ORCAD library symbol
Section8.3 Terms and acronyms:
Added acronym for TR, SR, and HR
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WCD9335 Audio Codec Device Specification (Advance Information) Introduction
1 Introduction
1.1 WCD9335 detailed functional block diagram
I2C_SCL
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primOarpyti/osnpaelUafokltreraorstmhoeiucrndmic DDMMIICC33__DCALKTA ddmmiicc56 hBeaMattdueslrtyeibtmuctootonnnittroorl JTAG RxI2Sinterface RRRXXX___II22I2SSS___SSWCDKS1
(MBHC)
PrimSapryeaHkSermmicic22/ DMIC2_DATA DMIC dmic4 Hi-Fiaudio JTDI,JTDO,JTMS,JTCK,JTRST
OptionalPrimSapryeaHkSermmicic33/ DMIC2_CLK interfaces dmic3 recording VDD_TX 1.8V
DMIC1_DATA dmic2 VDD_RX
SVAmic/PrimaryHSmic1/ DMIC1_CLK dmic1 VDD_IO 1.8V
Speakermic1 VDD_MX
PPDDMM__DCALKTA DigSiinotatuelnrIdf/awOciesre StereohybridANC SidetoneIIR Processingengine SBIuDcOk VOVUVGVATSNDU_WDDAX_____SSSSSIIIIIDDDDDOOOOO 1.8VVDD_A_LV,
s VOUT_D_SIDO VDD_MX
sWWpeSSaAkEAea88rrp8a8iem11c0ep5s/ EEAARROOPM AnalogoutpDuAtsC dac1 pRroxcdeisgsitianlg portcircuit VVDDDD__CAO_RLPVEVAD_DV_PBGOUNSCDKs
Headset HHPPHH__LREF DAC dac2 RxInmteurpxo/lamtoixrisng Sup SBMuPckS VVGOSNUWDT___BBBUUUCCCKKK 1.8V
HPH_R DAC dac3 coSnavemrpteler(rSaRteC) PA_VNEG
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perforammapnlcifeieprlfaoyrbhaigchk LLIINNEE__OOUUTT22__MP DAC dac5 Filtering BGVref GND_CCCCOOMMPP
Class-Hcontrol
toPMI8994Hapticsdriver LINE_OUT3 DAC dac6 Ultrasonic VABDACT VBAT_ADC_IN VBAT
LINE_OUT_REF proximitytone VDD_MIC_BIAS
Utrlatrnassdouucnedr LINE_OUT4 DAC dac7 SLIMbguesne/rI2aStorbridge LMDIOC-HbiVas& MICMBIC__CBFIIALLSTD_xOR(xE_4HF) VPMH_ICPW_RB_IBABSYxP(x4)
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WCD9335 Audio Codec Device Specification (Advance Information) Introduction
1.2 Features
Feature WCD9335 capabilities
System
Hi-Fi audio Recording path: 110 dB dynamic range and -100 dB THD+N
Playback path: 130 dB dynamic range and -110 dB THD+N
Qualcomm Snapdragon Voice Microphone activity detection (MAD) to detect audio, ultrasound, and beacon activity
Activation subsystem Codec processing engine (CPE) with 304 kB on-chip RAM
Provides keyword detection and user identification in the codec with less than 1mA
power at battery (100% speech occupancy)
Look-ahead buffer provides more seamless interaction to users
Digital I/Os
SLIMbus slave Two data lanes; 16 Tx ports + 8 Rx ports + control
Tx sample rates: 8, 16, 32, 44.111, 48, 96 and 192 kHz
Rx sample rates: 8, 16, 32, 44.1, 48, 96, 192, and 384 kHz
Bit resolution: 12, 16, 20, 24, 32
Framer device to support framer handover to codec
Two stereo master & slave I2S Isochronous mode
Push/pull transport protocols
Internal FLL; SLIMbus to I2S bridge
Four Tx ports + four Rx ports
Rx/Tx sampling rates: 8, 16, 32, 44.1, 48, 96, and 192 kHz
Bit resolution: 16 and 32
Soundwire interface to Multi-channel, audio and control using two lines (one clock and one data)
WSA8810/WSA8815
Digital microphone ports Six; three clock lines; nine supported frequencies from 600 kHz to 6.144MHz
Interrupts Multiple hardware interrupts multiplexed behind two interrupt pins
Tx processing
Analog audio input ports Six that support differential and single-ended configurations
Three different operational modes:
Hi-Fi
Programmable gain from 0–24 dB in 1.5 dB steps
0.7 µVrms input referred noise, 101 dB SNR and -104 THD at 21 dB gain
Standard
Programmable gain from 0–30 dB in 1.5 dB steps
1.7 µVrms input referred noise, 94 dB SNR and -100 THD at 21 dB gain
Ultra low-power
Programmable gain from 0–30 dB in 1.5 dB steps
3 µVrms input referred noise, 89 dB SNR and -97 THD at 21 dB gain
Capless inputs
Input multiplexing allows routing any AMIC input to any decimator
Integrated IEC diodes on AMIC2_INP, AMIC3_INP, and AMIC4_INP
ADCs Seven (six audio ADCs, and one VBAT ADC)
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WCD9335 Audio Codec Device Specification (Advance Information) Introduction
Feature WCD9335 capabilities
Concurrency Nine concurrent Tx decimation paths to support voice, audio, and ultrasound
applications
Digital controls Automatic peak control avoids digital hard clipping
Gain: -84 to +40 dB in 0.5 dB increments
DC blocking corner frequency: 4, 75, and 100 Hz
Decimation filters Nine decimation filters for concurrent Tx paths
Passband ripple: ± 0.005 dB
Rx processing
Analog audio output ports Seven – earpiece, stereo headphone, four line outputs (two differential, two
single-ended or four single-ended)
Integrated IEC diodes on EAROP, EAROM, HPH_L, HPH_R, and HPH_REF pins
Class-H differential earpiece output
125 mW (typical) into 32 Ω; 150 mW (minimum) into 16 or 10.67 Ω
Class-H stereo single-ended headphone outputs; capless; 16 or 32 Ω
Two differential and two single-ended line outputs
Digital audio to WSA Soundwire interface
Four-level SmartBoost, two per channel
DACs Seven DACs and nine dedicated interpolators
High-performance DACs for differential line outputs (to external headphone amps)
Performance Headphone: 1 Vrms; 123 dB dynamic range, -105 dB THD+N and 10 µVpp click and
pop in Class-H mode
Line outputs: 2 Vrms; 130 dB dynamic range and -110 THD+N (differential)
Concurrency Nine concurrent Rx paths
Frequency response Highpass filter (HPF) cutoff of 0.48 Hz with 0.0025 dB droop at 20 Hz to meet Dolby
requirements
Nine interpolation filters with passband ripple of ±0.0025 dB (HPF disabled)
Mixing Digital mixing at the input of each DAC path
Digital mixing on inputs to IIRs with independent gain control
HD audio and ultrasound mixing path added to all interpolators
Proximity-pattern multiplexer added to ear mixing path
Dynamic range enhancement DRE provides Hi-Fi audio quality for headphone and line-output PAs
Protection and suppression Over-current protection
Click-and-pop suppression
Multiple sample rates Any path may use any of these sampling rates: 8, 16, 32, 44.1, 48, 96, and 192, and
384 kHz
Concurrent PCM rates Independent rates on each path to support voice, music, and ultrasonic concurrently
Additional digital processing and paths
Active noise cancellation Stereo hybrid ANC selectable from any ADC or digital microphone (DMIC)
Supports feed-forward, feedback, and adaptive modes
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