VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design

363 Pages·1996·15.902 MB·

by  Prof. Dr. Ulrich Golze (auth.)

VLSI Chip Design with the
Hardware Description Language VERILOG
Springer-Verlag Berlin Heidelberg GmbH
Ulrich Golze
VLSI Chip Design
with the
Hardware Description
Language VERILOG
An Introduction Based on
a Large RISe Processor Design
With Peter Blinzer, Elmar Cochlovius,
Michael Schafers, and Klaus-Peter Wachsmann
Springer
Prof. Dr. Ulrich Golze
Department of Integrated Circuit Design (E.I.S.)
Technical University of Braunschweig
P.O. Box 33 29
D-38023 Braunschweig, Germany
E-mail: [email protected]
Ulrich Golze received a Diploma in Mathematics and a PhD in Computer Science at the
University of Hannover, Germany, an M.A. of Computer and Communication Sciences
at the University of Michigan, Ann Arbor, Michigan, USA, and an M.B.A. of Business
Administration at the European Business School INSEAD in Fontainebleau, France.
With 176 Figures and 80 Tables
Includes Diskette
ISBN 978-3-642-64650-8 ISBN 978-3-642-61001-1 (eBook)
DOI 10.1007/978-3-642-61001-1
Additional material to this book can be downloaded from http://extras.springer.com
Library of Congress Cataloging-in-Publication Data applied for
Die Deutsche Bibliothek - CIP-Einheitsaufnahme
VLSI chip design with the hardware description language
VERI LOG : an introduction based on a large RISC processor
design I Ulrich Golze. - Berlin; Heidelberg; New York; .
Barcelona; Budapest; Hong Kong; London; Milan; Paris;
Santa Clara; Singapore; Tokyo: Springer.
NE: Golze, Ulrich
Buch, - 1996
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© Springer-Verlag Berlin Heidelberg 1996
Softcover reprint of the hardcover 1st edition 1996
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even in the absence of a specific statement, that such names are exempt from the relevant
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Typesetting: Camera ready by author
SPIN 10502185 45/3142 - 5 432 1 0 - Printed on acid-free paper
Preface
The art of transforming a circuit idea into a chip has changed permanently.
Formerly, the electrical, physical, and geometrical tasks were predominant.
Later, mainly net lists of gates had to be constructed. Nowadays, designing
with hardware description languages (HDL) similar to programming lan
guages is at the center of digital circuit design. HDL based design is one of the
centers of this book.
The successful design of small circuits is no problem today, but the demands
on a design team are high when designing large real circuits. The second
center is therefore a complete design of a real modern RISC processor with an
efficiency in the range of a SPARC.
After an introduction also considering the economic importance of chip design
as a key technology, Chapter 2 gives an overview of VLSI design (Very Large
Scale Integration). The third chapter leads to modern RISC processors and
prepares coarse design decisions. Due to the central role of hardware descrip
tion languages, Chapter 4 contains a short and Chapter 11 an extensive intro
duction to the HDL VERILOG and to typical modeling techniques. Numerous
examples as well as a VERILOG simulator are included on the disk.
The RISC processor TOOBSIE to be designed is specified externally in Chapter 5
by its behavior, its instructions, and an HDL interpreter as a reference. The
internal specification in the next chapter determines a coarse architecture.
The central HDL model is the Coarse Structure Model that is completely and
executably included on the disk in 013. The datapath pipeline of this model is
explained in Chapter 7.
The Coarse Structure Model is suited for a semi-automatic translation int.o a
Gate Model based on the component library of the silicon vendor. This Gate
Model will be synthesized in Chapter 8 using selected examples. Finally,
Chapter 9 treats the subjects testing, testability, tester, and testboard and
discloses, whether the produced processor is actually functioning. A general
outline concludes the volume.
vi Preface
This book is addressed to computer scientists and electrical engineers, but also
managers, hence to practitioners designing chips or considering their appli
cation. It introduces
• modern VLSI design;
• semi-custom design of large chips;
• the hardware description language VERILOG HDL;
• the design of a modern real RISC processor;
• HDL modeling of large designs;
• specification, behavior, structure, HDL model, gate model, test, and
testability.
As a textbook, this volume is self-contained and complete. Experts, however,
may want to understand the RISC processor design at selected points or even
completely, possibly as a base for the development of their own CAD tools and
design methods. For this expert, there is an expert volume also containing all
graphical "schematics" of the Gate Model (p. 359).
Figures and tables are numbered together per chapter. Chapter numbers
beginning with an H such as H5.3 refer to the more hardware-oriented expert
volume.
The Team of a Large Project
A project of this size is developed in a team, even worse, in a changing team.
The figure on the next page shows a hierarchy without "up" and "down", and
every level without a first or last position. Without the assistants of the second
ring, the project would not have been accomplished. The students of the third
ring were particularly engaged. Peter Blinzer has moved by unusual commit
ment from the outer to the middle ring.
It all began with an idea of Michael Schafers, which the author declared as
impractical, not only for reasons of cost. He developed together with Klaus
Peter Wachs mann the training processor and predecessor TOOBSIE1. Later,
the daily project management was done by Michael Schafers and also by Klaus
Peter Wachsmann. Together with Elmar Cochlovius joining the team later,
they have worked out the external and internal specification with all archi
tectural details (Chapters 5 and 6).
The documentation of a large project is often unpopular, but often also decisive
for the project. Elmar Cochlovius has managed (not (mly) this task; he was
documenting by himself, and - more difficult - has motivated others to prepare
Preface vii
documentation as a base for this book. In addition to the practical chip design,
all three assistants have performed PhD research on design methodology
(Chapter 10). As just one example, we mention the research of Elmar
Cochlovius on high-level specification with statecharts.
-g. .
g..
ID
(\)
Peter Blinzer, Rudiger Bodack, Klaus Meyer, and Sebastian Steibl have worked
out the VERILOG models, in particular the Coarse Structure Model, and have
commented on them (Chapters 7, H3, H4, ~2, and 03). Peter Blinzer was also
the major force for the Gate Model (Chapters 8 and H5).
Gerrit Telkamp has designed simple and complicated testboards and has tested
the processor in the tester and on the board. Together with Peter Blinzer, he
has prepared Chapter 9 on test. The latter has worked out the production test.
Claude Ackad has prepared as a book within the book the extensive VERILOG
introduction (Chapters 4 and 11) and has become unpopular as a quality
assurer of our documentation. Thomas Scholz designed operating systems for
various testboards.
Matthias Bodenstein did not lose his joy in designing graphics until the last
figure. Jiirgen Hannken-Illjes transformed technical schematics into print
able figures using methods of pattern recognition.
Karsten Dageforde, Matthias Mansfeld, Gerrit Mierse, Frank Prielipp, Jorg
Reitner, Heiko Stuckenberg, Dirk Wodtke, and Florian Buchholz have delivered
important contributions on the (invisible) fourth ring.
viii Preface
The project was performed at the Department of Integrated Circuit Design
(E.I.S.) at the Technical University of Braunschweig. It was enabled by the
support of LSI Logic Corp., the ESPRIT project EUROCHIP, the Lower Saxony
Ministery of Science and Culture (MWK) and the Federal Ministery of Edu
cation and Science (BMBW), and a Volkswagen grant.
We are especially grateful to Wellspring Solutions Corp. for offering the
simulator VeriWell to the readers of this book. It is included on the disk without
any warranty; there are no restrictions on the use and application purpose.
Without encouragement and criticism of my publisher Springer, this work
would not have been completed.
I started learning German at the age of 1 or so, English at 10, and began to
prefer American at 24 when studying at the University of Michigan.
Unfortunately, it will never be possible to make up for this delay of 9 years. I
apologize for all those phrases that you as the reader would have expressed
more smoothly.
Formerly, I doubted the value of dedications in books, until I myself started
neglecting my family for my book: for Barbara, Christian, and Fabian.
Braunschweig, September 1995 Ulrich Golze
Contents
1 Introduction .................................................................................. 1
2 :Design ofVLSI Circuits .................................................................. 9
2.1 Technological Foundations and Design Styles .. .... .... .......................... 9
2.2 The Design Process ........................................................................ 14
2.3 The Design Phases ......................................................................... 17
3 RISC Architectures........................ ....... ........ ..................... ............ 25
3.1 A Simple RISC Processor ................................................................ 27
3.2 Selection of a Processor Architecture ................................................ 31
3.2.1 Proposals for Architectural Extensions ................................. 32
3.2.2 Evaluation of Proposals ........................................................ 34
3.2.3 Summary of Extensions Accepted ......................................... 36
4 Short Introduction to VERILOG ....................................................... 39
5 ExtemalSpecificationofBehavior .................................................... 47
5.1 The RISC Processor at Work ............................................................ 48
5.1.1 The Assembler ................................................................... 48
5.1.2 The Testboard ..................................................................... 49
5.2 The Instruction Set ......................................................................... 49
5.2.1 Class LD/ST of Load and Store Instructions ............................ 52
5.2.2 Class eTR of Branch Instructions ......................................... 53
5.2.3 Class ALU of Arithmetic and Logic Instructions ..................... 55
5.2.4 Instructions of Class Special ................................................ 56
5.2.5 Synthetic Instructions ......................................................... 57
5.2.6 External Specification ofInterrupts ...................................... 57
5.3 An Interpreter as a VERILOG HDL Model ........................................ 59
5.3.1 Overview ............................................................................ 61
5.3.2 Components ....................................................................... 63
5.3.3 Application ........................................................................ 66
5.4 Specification of Test Strategy ............................................................ 69
5.5 Quantitative Specifications .............................................................. 70