VHDL Tutorial

94 Pages·2009·0.12 MB·English

VHDL Tutorial

Presenter : Ravi Saini

IC Design Group
CEERI, Pilani - 333 031
Rajasthan, India

Tel : [phone]
E-Mail :
Model of a Hardware in VHDL

A hardware model in VHDL is described in two parts, the entity
declaration part and the associated architecture body part.

ENTITY

BODY 1 BODY 2 BODY N

The entity declaration gives a name to the model being developed and
also declares its external interface signals (called ports) : their names,
modes (in, out, inout, buffer) and their types.
IDG, CEERI, Pilani.
What is Synthesis?

Synthesis is the process of constructing a gate-level netlist from a model
of a circuit described in VHDL.

A synthesis program generates a RTL netlist (FF’s, ALU, multiplexer,
interconnected by wires). So, the RTL module builder is necessary and
the purpose of this builder is to build each of the required RTL blocks
from a library of predefined components (user-specified target
technology).

After producing a gate-level netlist, a logic optimizer reads in this netlist
and optimizes the circuit for the user-specified area and timing
constraints.

IDG, CEERI, Pilani.
VHDL model

Synthesis
RTL module Area and
builder Timing constraints
Target
technology
Unoptimized Logic optimizer
Gate level netlist
Optimized
Gate level netlist
The synthesis process
IDG, CEERI, Pilani.
Literals
Values
(enumeration, integer, ….)
(logic-0, logic-1, don’t-care,

floating, unknown)

Data types

(enumeration types, record types,….)
Elements

(wire, latch, flip-flop,
Data objects
ALU, multiplexer,……)
(variables, constants, signals)

Statements
(signal assignment, if, case, ……)

Structure

(process, block, component, …..)

Hardware world
VHDL world
IDG, CEERI, Pilani.
Questions to ask are:

• How are literals mapped to logic values?

• How does a data type translate to hardware?

• How do data objects map to hardware?

• How are statements translated to hardware?
IDG, CEERI, Pilani.
Synthesis in a design process

Circuit

Models

Style A Style B Style C Style D

A circuit can be described in many different ways, not all of which may
be synthesizable. This is due to the fact that VHDL was designed
primarily as simulation language and not for synthesis.

There is no standardized subset of VHDL for synthesis.
There is no direct object in VHDL that means a latch or a flip-flop,
therefore, each synthesis system provide different mechanism to model
a flip-flop or a latch.
IDG, CEERI, Pilani.
Value Holders for Hardware Modeling

VHDL provides two classes of data objects, signal and variable, that
can be used to model the basic value holders in hardware.

The basic value holders in hardware are

• Wire
• Flip-flop (an edge-triggered device)
• Latch (a level-sensitive device)
IDG, CEERI, Pilani.
In VHDL, a signal, or a variable declared in a process, retains its value
through the entire simulation run, thus inferring memory.

Example :

signal A, B, C, Z : bit;
…….

No_memory : process(A, B, C)
variable temp : bit;
begin
temp := A and B;
Z <= temp or C;
end process;

VHDL semantics says that variable temp retains its value through the
entire simulation run.
IDG, CEERI, Pilani.
Logic generated after synthesis is

temp
A
Z

B

C
IDG, CEERI, Pilani.