Very Low Power, Negative Rail Input, Rail-to-Rail Output, Fully Differential Amp datasheet

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THS4521,THS4522,THS4524
SBOS458H–DECEMBER2008–REVISEDJUNE2015
THS452x Very Low Power, Negative Rail Input, Rail-To-Rail Output, Fully Differential
Amplifier
1 Features 3 Description
• FullyDifferentialArchitecture The THS4521, THS4522, and THS4524 family of
1 devices are very low-power, fully differential
• Bandwidth:145MHz(A =1V/V)
V amplifiers with rail-to-rail output and an input
• SlewRate:490V/μs common-mode range that includes the negative rail.
• HD :–133dBcat10kHz(1V ,R =1kΩ) These amplifiers are designed for low-power data
2 RMS L
acquisition systems and high-density applications
• HD :–141dBcat10kHz(1V ,R =1kΩ)
3 RMS L where power dissipation is a critical parameter, and
• InputVoltageNoise:4.6nV/√Hz(f=100kHz) provide exceptional performance in audio
• THD+N:–112dBc(0.00025%)at1kHz(22-kHz applications.
BW,G=1,5V )
PP The family includes single FDA (THS4521), dual FDA
• Open-LoopGain:119dB(DC) (THS4522),andquadFDA(THS4524)versions.
• NRI—NegativeRailInput
DeviceInformation(1)
• RRO—Rail-to-RailOutput
PARTNUMBER PACKAGE BODYSIZE(NOM)
• Output Common-ModeControl(withLowOffset)
SOIC(8) 4.90mm×3.91mm
• PowerSupply: THS4521
VSSOP(8) 3.00mm×3.00mm
– Voltage:+2.5V(±1.25V)to+5.5V(±2.75V)
THS4522 TSSOP(16) 5.00mm×4.40mm
– Current:1.14mA/ch
THS4524 TSSOP(38) 9.70mm×4.40mm
• Power-DownCapability:20μA(typical)
(1) Forallavailablepackages,seethepackageoptionaddendum
attheendofthedatasheet.
2 Applications
• Low-PowerSARandΔΣ ADCDrivers
• Low-PowerDifferentialDrivers
• Low-PowerDifferentialSignalConditioning
• Low-Power, High-PerformanceDifferentialAudio
Amplifiers
THS4521andADS1278CombinedPerformance
1 kΩ 1-kHz FFT
0
1.5 nF G = 1
-20 RF= RG= 1 kΩ
5 V C = 1.5 nF
F
-40 V = 5 V
1 kΩ 49.9Ω BFS) -60 LoSad = 2.2 nF
VVIINN-+ 1 kΩ THS4521 49.9Ω 2.2 nF ADAASIINN1NP27118(CVHCO 1M) Magnitude (d -1-0800
VOCM -120
x1
0.1μF 0.1μF -140
1/2
OPA2350
-160
1.5 nF
0 4 8 12 16 20 24 26
Frequency (kHz)
1 kΩ
Tone Signal SINAD SFDR
(Hz) (dBFS) SNR (dBc) THD (dBc) (dBc) (dBc)
1 k -0.50 109.1 -107.9 105.5 113.7
Formoreinformationonthiscircuit,viewSBAU197.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
THS4521,THS4522,THS4524
SBOS458H–DECEMBER2008–REVISEDJUNE2015 www.ti.com
Table of Contents
1 Features.................................................................. 1 8.3 FeatureDescription.................................................25
2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................34
3 Description............................................................. 1 8.5 Programming...........................................................40
4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 41
9.1 ApplicationInformation............................................41
5 DeviceComparisonTable..................................... 3
9.2 TypicalApplications ...............................................41
6 PinConfigurationandFunctions......................... 4
10 PowerSupplyRecommendations..................... 51
7 Specifications......................................................... 7
11 Layout................................................................... 51
7.1 AbsoluteMaximumRatings......................................7
11.1 LayoutGuidelines.................................................51
7.2 ESDRatings ............................................................7
11.2 LayoutExample....................................................52
7.3 RecommendedOperatingConditions.......................7
12 DeviceandDocumentationSupport................. 53
7.4 ThermalInformation..................................................7
7.5 ElectricalCharacteristics:V –V =3.3V............8 12.1 DeviceSupport......................................................53
S+ S–
7.6 ElectricalCharacteristics:V –V =5V.............10 12.2 RelatedLinks........................................................53
S+ S–
7.7 TypicalCharacteristics............................................12 12.3 CommunityResources..........................................53
7.8 TypicalCharacteristics:V –V =3.3V..............14 12.4 Trademarks...........................................................53
S+ S–
7.9 TypicalCharacteristics:5V....................................19 12.5 ElectrostaticDischargeCaution............................53
12.6 Glossary................................................................53
8 DetailedDescription............................................ 24
13 Mechanical,Packaging,andOrderable
8.1 Overview.................................................................24
Information........................................................... 53
8.2 FunctionalBlockDiagram.......................................25
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionG(December2014)toRevisionH Page
• ChangedcapacitorunitsinfrontpagediagramfrommFtoµF(typo)................................................................................... 1
• ChangedRFandRGunitinfrontpageFFTplotfromkWtokΩ(typo)................................................................................. 1
• ChangedAbsoluteMaximumRatingsminimumstoragetemperaturevaluefrom65to–65(typo) ..................................... 7
• AddedCommunityResourcessection................................................................................................................................. 53
ChangesfromRevisionF(September2011)toRevisionG Page
• AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional
Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device
andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1
ChangesfromRevisionE(December2010)toRevisionF Page
• ChangedInputOffsetCurrentvaluesin3.3VElectricalCharacteristics............................................................................... 8
• ChangedInputOffsetCurrentDriftvaluesin3.3VElectricalCharacteristics....................................................................... 8
• ChangedInputOffsetCurrentvaluesin5VElectricalCharacteristics................................................................................ 11
• ChangedInputOffsetCurrentDriftvaluesin5VElectricalCharacteristics........................................................................ 11
• ChangedR41andR42inFigure79..................................................................................................................................... 42
ChangesfromRevisionD(August2010)toRevisionE Page
• Changedtestlevelindicationfor5-VinputoffsetvoltagedriftfromBtoC.......................................................................... 10
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5 Device Comparison Table
These fully differential amplifiers feature accurate output common-mode control that allows for dc-coupling when
driving analog-to-digital converters (ADCs). This control, coupled with an input common-mode range below the
negative rail as well as rail-to-rail output, allows for easy interfacing between single-ended, ground-referenced
signal sources. Additionally, these devices are ideally suited for driving both successive-approximation register
(SAR)anddelta-sigma(ΔΣ)ADCsusingonlyasingle+2.5Vto+5Vandgroundpower supply.
The THS4521, THS4522, and THS4524 family of fully differential amplifiers is characterized for operation over
the full industrial temperature range from –40°C to +85°C. Table 1 shows a comparison of the THS4521 device
tosimilarTI devices.
Table1.THS4521DeviceComparison
BW I THD(dBc) V DUALPART
Q N
DEVICE (MHz) (mA) AT100kHz (nV/√Hz) RAIL-TO-RAIL NUMBERS
THS4531 36 0.25 –104 10.0 NegIn,Out —
THS4521 145 0.95 –102 4.6 NegIn,Out THS4522
THS4520 620 14.2 –107 2.0 Out —
THS4541 850 10.1 –137 2.2 NegIn,Out —
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6 Pin Configuration and Functions
THS4521DandDGKPackage
8-PinSOICandVSSOP THS4524DBTPackage
TopView 38-PinTSSOP
TopView
V 1 8 V
IN- IN+ PD1 1 38 VS-
V 2 7 PD
OCM VIN1+ 2 37 VOUT1-
V 3 6 V
S+ S- VIN1- 3 36 VOUT1+
V 4 5 V
OUT+ OUT- VOCM1 4 35 VS1+
VS- 5 34 VS-
THS4522PWPackage PD2 6 33 VS-
16-PinTSSOP
TopView VIN2+ 7 32 VOUT2-
VIN2- 8 31 VOUT2+
PD1 1 16 VS- VOCM2 9 30 VS2+
VIN1+ 2 15 VOUT1- VS- 10 29 VS-
VIN1- 3 14 VOUT1+ PD3 11 28 VS-
VOCM1 4 13 VS1+ VIN3+ 12 27 VOUT3-
PD2 5 12 VS- VIN3- 13 26 VOUT3+
VIN2+ 6 11 VOUT2- VOCM3 14 25 VS3+
VIN2- 7 10 VOUT2+ VS- 15 24 VS-
VOCM2 8 9 VS2+ PD4 16 23 VS-
VIN4+ 17 22 VOUT4-
VIN4- 18 21 VOUT4+
VOCM4 19 20 VS4+
PinFunctions:THS4521
PIN
DESCRIPTION
NAME NO.
V 1 Invertingamplifierinput
IN–
V 2 Common-modevoltageinput
OCM
V 3 Amplifierpositivepower-supplyinput
S+
V 4 Noninvertingamplifieroutput
OUT+
V 5 Invertingamplifieroutput
OUT–
V 6 Amplifiernegativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
PD 7 Powerdown.PD=logiclowputsdeviceintolow-powermode.PD=logichighoropenfornormaloperation.
V 8 Noninvertingamplifierinput
IN+
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PinFunctions:THS4522
PIN
DESCRIPTION
NAME NO.
PD 1 Powerdown1.PD=logiclowputsdeviceintolow-powermode.PD=logichighoropenfornormaloperation.
1
V 2 Noninvertingamplifier1input
IN1+
V 3 Invertingamplifier1input
IN1–
V 4 Common-modevoltageinput1
OCM1
PD 5 Powerdown2.PD=logiclowputsdeviceintolow-powermode.PD=logichighoropenfornormaloperation.
2
V 6 Noninvertingamplifier2input
IN2+
V 7 Invertingamplifier2input
IN2–
V 8 Common-modevoltageinput2
OCM2
V 9 Amplifier2positivepower-supplyinput
S+2
V 10 Noninvertingamplifier2output
OUT2+
V 11 Invertingamplifier2output
OUT2–
V 12 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 13 Amplifier1positivepower-supplyinput
S+1
V 14 Noninvertingamplifier1output
OUT1+
V 15 Invertingamplifier1output
OUT1–
V 16 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
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PinFunctions:THS4524
PIN
DESCRIPTION
NAME NO.
PD 1 Powerdown1.PD=logiclowputschannelintolow-powermode.PD=logichighoropenfornormaloperation.
1
V 2 Noninvertingamplifier1input
IN1+
V 3 Invertingamplifier1input
IN1–
V 4 Common-modevoltageinput1
OCM1
V 5 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
PD 6 Powerdown2.PD=logiclowputschannelintolow-powermode.PD=logichighoropenfornormaloperation.
2
V 7 Noninvertingamplifier2input
IN2+
V 8 Invertingamplifier2input
IN2–
V 9 Common-modevoltageinput2
OCM2
V 10 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
PD 11 Powerdown3.PD=logiclowputschannelintolow-powermode.PD=logichighoropenfornormaloperation.
3
V 12 Noninvertingamplifier3input
IN3+
V 13 Invertingamplifier3input
IN3–
V 14 Common-modevoltageinput3
OCM3
V 15 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
PD 16 Powerdown4.PD=logiclowputschannelintolow-powermode.PD=logichighoropenfornormaloperation.
4
V 17 Noninvertingamplifier4input
IN4+
V 18 Invertingamplifier4input
IN4–
V 19 Common-modevoltageinput4
OCM4
V 20 Amplifier4positivepower-supplyinput
S4+
V 21 Noninvertingamplifier4output
OUT4+
V 22 Invertingamplifier4output
OUT4–
V 23 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 24 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 25 Amplifier3positivepower-supplyinput
S3+
V 26 Noninvertingamplifier3output
OUT3+
V 27 Invertingamplifier3output
OUT3–
V 28 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 29 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 30 Amplifier2positivepower-supplyinput
S2+
V 31 Noninvertingamplifier2output
OUT2+
V 32 Invertingamplifier2output
OUT2–
V 33 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 34 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
V 35 Amplifier1positivepower-supplyinput
S1+
V 36 Noninvertingamplifier1output
OUT1+
V 37 Invertingamplifier1output
OUT1–
V 38 Negativepower-supplyinput.NotethatV istiedtogetheronmulti-channeldevices.
S– S–
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7 Specifications
7.1 Absolute Maximum Ratings
Overoperatingfree-airtemperaturerange(unlessotherwisenoted).(1)
MIN MAX UNIT
Supplyvoltage,VS–toVS+ 5.5 V
Input/outputvoltage,VI(VIN±,VOUT±,VOCMpins) (VS–)–0.7 (VS+)+0.7 V
Differentialinputvoltage,VID 1 V
Outputcurrent,IO 100 mA
Inputcurrent,II(VIN±,VOCMpins) 10 mA
Continuouspowerdissipation SeeThermalInformationtable
Maximumjunctiontemperature,TJ 150 °C
Maximumjunctiontemperature,TJ(continuousoperation,long-termreliability) 125 °C
Operatingfree-airtemperature,TA –40 85 °C
Storagetemperature,Tstg –65 150 °C
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended
OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
7.2 ESD Ratings
VALUE UNIT
Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±1300
V Electrostatic Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101,allpins(2) ±1000 V
(ESD) discharge
Machinemodel(MM) ±50
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
7.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
V single-supplyvoltage 2.7 5.0 5.4 V
S+
T Ambienttemperature –40 25 85 °C
A
7.4 Thermal Information
THS4521 THS4522 THS4524
THERMALMETRIC(1) D DGK PW DBT UNIT
8PINS 8PINS 16PINS 38PINS
R Junction-to-ambientthermalresistance 127.8 193.8 124.2 106.2
θJA
R Junction-to-case(top)thermalresistance 81.8 84.1 62.8 60.9
θJC(top)
R Junction-to-boardthermalresistance 68.3 115.3 68.5 65.5
θJB
°C/W
ψ Junction-to-topcharacterizationparameter 32.2 17.9 15.8 18.5
JT
ψ Junction-to-boardcharacterizationparameter 67.8 113.6 68 65.1
JB
R Junction-to-case(bottom)thermalresistance N/A N/A N/A N/A
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
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7.5 Electrical Characteristics: V – V = 3.3 V
S+ S–
AtV =3.3V,V =0V,V =open,V =2V (differential),R =1kΩdifferential,G=1V/V,single-endedinput,
S+ S– OCM OUT PP L
differentialoutput,andinputandoutputreferencedtomidsupply,unlessotherwisenoted.
TEST
PARAMETER TESTCONDITIONS LEVEL(1) MIN TYP MAX UNIT
ACPERFORMANCE
VOUT=100mVPP,G=1 C 135 MHz
VOUT=100mVPP,G=2 C 49 MHz
Small-signalbandwidth
VOUT=100mVPP,G=5 C 18.6 MHz
VOUT=100mVPP,G=10 C 9.3 MHz
Gainbandwidthproduct VOUT=100mVPP,G=10 C 93 MHz
Large-signalbandwidth VOUT=2VPP,G=1 C 95 MHz
Bandwidthfor0.1-dBflatness VOUT=2VPP,G=1 C 20 MHz
Risingslewrate(differential) VOUT=2-VStep,G=1,RL=200Ω C 420 V/μs
Fallingslewrate(differential) VOUT=2-VStep,G=1,RL=200Ω C 460 V/μs
Overshoot VOUT=2-VStep,G=1,RL=200Ω C 1.2%
Undershoot VOUT=2-VStep,G=1,RL=200Ω C 2.1%
Risetime VOUT=2-VStep,G=1,RL=200Ω C 4 ns
Falltime VOUT=2-VStep,G=1,RL=200Ω C 3.5 ns
Settlingtimeto1% VOUT=2-VStep,G=1,RL=200Ω C 13 ns
HARMONICDISTORTION
f=1MHz,VOUT=2VPP,G=1 C –85 dBc
2ndharmonic f=1kHz,VOUT=1VRMS,G=1(2), C –133 dBc
differentialinput
f=1MHz,VOUT=2VPP,G=1 C –90 dBc
3rdharmonic f=1kHz,VOUT=1VRMS,G=1(2), C –141 dBc
differentialinput
Second-orderintermodulationdistortion Two-tone,f1=2MHz,f2=2.2MHz, C –83 dBc
VOUT=2-VPPenvelope
Third-orderintermodulationdistortion Two-tone,f1=2MHz,f2=2.2MHz, C –90 dBc
VOUT=2-VPPenvelope
Inputvoltagenoise f>10kHz C 4.6 nV/√Hz
Inputcurrentnoise f>100kHz C 0.6 pA/√Hz
Overdriverecoverytime Overdrive=±0.5V C 80 ns
Outputbalanceerror VOUT=100mV,f≤2MHz(differentialinput) C –57 dB
Closed-loopoutputimpedance f=1MHz(differential) C 0.3 Ω
Channel-to-channelcrosstalk(THS4522,
f=10kHz,measureddifferentially C –125 dB
THS4524)
DCPERFORMANCE
Open-loopvoltagegain(AOL) A 100 116 dB
TA=+25°C A ±0.2 ±2 mV
Input-referredoffsetvoltage
TA=–40°Cto+85°C B ±0.5 ±3.5 mV
Inputoffsetvoltagedrift(3) TA=–40°Cto+85°C C ±2 μV/°C
Inputbiascurrent(4) TA=+25°C B 0.65 0.85 μA
TA=–40°Cto+85°C B 0.75 0.95 μA
Inputbiascurrentdrift(3) TA=–40°Cto+85°C B ±1.75 ±2 nA/°C
TA=+25°C B ±30 ±180 nA
Inputoffsetcurrent
TA=–40°Cto+85°C B ±30 ±215 nA
Inputoffsetcurrentdrift(3) TA=–40°Cto+85°C B ±100 ±600 pA/°C
(1) Testlevels:(A)100%testedat25°C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization
andsimulation.(C)Typicalvalueonlyforinformation.
(2) Notdirectlymeasurable;calculatedusingnoisegainof101asdescribedintheApplicationssection,AudioPerformance.
(3) Inputoffsetvoltagedrift,inputbiascurrentdrift,inputoffsetcurrentdrift,andV driftareaveragevaluescalculatedbytakingdataat
OCM
themaximum-rangeambient-temperatureendpoints,computingthedifference,anddividingbythetemperaturerange.Maximumdriftis
setbythedistributionofalargesamplingofdevices.Driftisnotspecifiedbyatestoraqualityassurance(QA)sampletest.
(4) Inputbiascurrentispositiveoutofthedevice.
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Electrical Characteristics: V – V = 3.3 V (continued)
S+ S–
AtV =3.3V,V =0V,V =open,V =2V (differential),R =1kΩdifferential,G=1V/V,single-endedinput,
S+ S– OCM OUT PP L
differentialoutput,andinputandoutputreferencedtomidsupply,unlessotherwisenoted.
TEST
PARAMETER TESTCONDITIONS LEVEL(1) MIN TYP MAX UNIT
INPUT
TA=+25°C A –0.2 –0.1 V
Common-modeinputvoltagelow
TA=–40°Cto+85°C B –0.1 0 V
TA=+25°C A 1.9 2 V
Common-modeinputvoltagehigh
TA=–40°Cto+85°C B 1.8 1.9 V
Common-moderejectionratio(CMRR) A 80 100 dB
Inputimpedance C 0.7pF kΩ∥pF
OUTPUT
TA=+25°C A 0.08 0.15 V
Outputvoltagelow
TA=–40°Cto+85°C B 0.09 0.2 V
TA=+25°C A 3.0 3.1 V
Outputvoltagehigh
TA=–40°Cto+85°C B 2.95 3.05 V
Outputcurrentdrive(forlinearoperation) RL=50Ω C ±35 mA
POWERSUPPLY
Specifiedoperatingvoltage B 2.5 3.3 5.5 V
TA=+25°C A 0.9 1.0 1.2 mA
Quiescentoperatingcurrent,perchannel
TA=–40°Cto+85°C B 0.85 1.0 1.25 mA
Power-supplyrejectionratio(±PSRR) A 80 100 dB
POWERDOWN
Enablevoltagethreshold Assuredonabove2.1V A 1.6 2.1 V
Disablevoltagethreshold Assuredoffbelow0.7V A 0.7 1.6 V
Disablepinbiascurrent C 1 μA
Power-downquiescentcurrent C 10 μA
Turn-ontimedelay TimetoVOUT=90%offinalvalue,VIN=2V, B 108 ns
RL=200Ω
Turn-offtimedelay TimetoVOUT=10%oforiginalvalue,VIN=2 B 88 ns
V,RL=200Ω
VOCMVOLTAGECONTROL
Small-signalbandwidth C 23 MHz
Slewrate C 55 V/μs
Gain A 0.98 0.99 1.02 V/V
Common-modeoffsetvoltagefromVOCMinput MVOeCaMsu=re1d.6a5tVVO±U0T.5wVithVOCMinputdriven, B ±2.5 ±4 mV
Inputbiascurrent VOCM=1.65V±0.5V B ±5 ±8 μA
VOCMvoltagerange A 1 0.8to2.5 2.3 V
Inputimpedance C 72∥1.5 kΩ∥pF
Defaultoutputcommon-modevoltageoffsetfrom
(VS+–VS–)/2 MeasuredatVOUTwithVOCMinputopen A ±1.5 ±5 mV
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7.6 Electrical Characteristics: V – V = 5 V
S+ S–
AtV =5V,V =0V,V =open,V =2V (differential),R =1kΩ,R =1kΩdifferential,G=1V/V,single-ended
S+ S– OCM OUT PP F L
input,differentialoutput,inputandoutputreferencedtomidsupply,unlessotherwisenoted.
TEST
PARAMETER TESTCONDITIONS LEVEL(1) MIN TYP MAX UNIT
ACPERFORMANCE
VOUT=100mVPP,G=1 C 145 MHz
VOUT=100mVPP,G=2 C 50 MHz
Small-signalbandwidth
VOUT=100mVPP,G=5 C 20 MHz
VOUT=100mVPP,G=10 C 9.5 MHz
Gainbandwidthproduct VOUT=100mVPP,G=10 C 95 MHz
Large-signalbandwidth VOUT=2VPP,G=1 C 145 MHz
Bandwidthfor0.1-dBflatness VOUT=2VPP,G=1 C 30 MHz
Risingslewrate(differential) VOUT=2-VStep,G=1,RL=200Ω C 490 V/μs
Fallingslewrate(differential) VOUT=2-VStep,G=1,RL=200Ω C 600 V/μs
Overshoot VOUT=2-VStep,G=1,RL=200Ω C 1%
Undershoot VOUT=2-VStep,G=1,RL=200Ω C 2.6%
Risetime VOUT=2-VStep,G=1,RL=200Ω C 3.4 ns
Falltime VOUT=2-VStep,G=1,RL=200Ω C 3 ns
Settlingtimeto1% VOUT=2-VStep,G=1,RL=200Ω C 10 ns
HARMONICDISTORTION
f=1MHz,VOUT=2VPP,G=1 C –85 dBc
2ndharmonic f=1kHz,VOUT=1VRMS,G=1(2), C –133 dBc
differentialinput
f=1MHz,VOUT=2VPP,G=1 C –91 dBc
3rdharmonic f=1kHz,VOUT=1VRMS,G=1(2), C –141 dBc
differentialinput
Second-orderintermodulationdistortion Two-tone,f1=2MHz,f2=2.2MHz, C –86 dBc
VOUT=2-VPPenvelope
Third-orderintermodulationdistortion Two-tone,f1=2MHz,f2=2.2MHz, C –93 dBc
VOUT=2-VPPenvelope
Inputvoltagenoise f>10kHz C 4.6 nV/√Hz
Inputcurrentnoise f>100kHz C 0.6 pA/√Hz
SNR VOUT=5VPP,20Hzto22kHzBW, C 123 dBc
differentialinput
THD+N f=1kHz,VOUT=5VPP,20Hzto22kHz C 112 dBc
BW,differentialinput
Overdriverecoverytime Overdrive=±0.5V C 75 ns
Outputbalanceerror VOUT=100mV,f<2MHz,VINdifferential C –57 dB
Closed-loopoutputimpedance f=1MHz(differential) C 0.3 Ω
Channel-to-channelcrosstalk(THS4522.THS4524) f=10kHz,measureddifferentially C –125 dB
DCPERFORMANCE
Open-loopvoltagegain(AOL) A 100 119 dB
TA=+25°C A ±0.24 ±2 mV
Input-referredoffsetvoltage
TA=–40°Cto+85°C B ±0.5 ±3.5 mV
Inputoffsetvoltagedrift(3) TA=–40°Cto+85°C C ±2 μV/°C
Inputbiascurrent(4) TA=+25°C B 0.7 0.9 μA
TA=–40°Cto+85°C B 0.9 1.1 μA
Inputbiascurrentdrift(3) TA=–40°Cto+85°C B ±1.8 ±2.2 nA/°C
(1) Testlevels:(A)100%testedat25°C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization
andsimulation.(C)Typicalvalueonlyforinformation.
(2) Notdirectlymeasurable;calculatedusingnoisegainof101asdescribedintheApplicationssection,AudioPerformance.
(3) Inputoffsetvoltagedrift,inputbiascurrentdrift,inputoffsetcurrentdrift,andV driftareaveragevaluescalculatedbytakingdataat
OCM
themaximum-rangeambient-temperatureendpoints,computingthedifference,anddividingbythetemperaturerange.Maximumdriftis
setbythedistributionofalargesamplingofdevices.Driftisnotspecifiedbyatestoraqualityassurance(QA)sampletest.
(4) Inputbiascurrentispositiveoutofthedevice.
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