Table Of ContentVERIFICATION BY ERROR MODELING
FRONTIERS IN ELECTRONIC TESTING
Consulting Editor
Vishwani D. Agrawal
Books in the series:
Verification by ErrorModeling
K. Radecka and Zilic
ISBN: 1-4020-7652-5
Elements of STIL: Principles and Applications of IEEE Std. 1450
G. Maston‚ T. Taylor‚ J. Villar
ISBN: 1-4020-7637-1
Fault Injection Techniques and Tools for Embedded systems Reliability
Evaluation
A. Benso‚ P. Prinetto
ISBN: 1-4020-7589-8
High Performance Memory Memory Testing
R. Dean Adams
ISBN: 1-4020-7255-4
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation
K. Chakrabarty
ISBN: 1-4020-7205-8
Test Resource Partitioning for System-on-a-Chip
K. Chakrabarty‚ Iyengar & Chandra
ISBN: 1-4020-7119-1
A Designers’ Guide to Built-in Self-Test
C. Stroud
ISBN: 1-4020-7050-0
Boundary-Scan Interconnect Diagnosis
J. de Sousa‚ P.Cheung
ISBN: 0-7923-7314-6
Essentials of Electronic Testing for Digital‚ Memory‚ and Mixed Signal VLSI Circuits
M.L. Bushnell‚ V.D. Agrawal
ISBN: 0-7923-7991-8
Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4
Test Standard
A. Osseiran
ISBN: 0-7923-8686-8
Design for At-Speed Test‚ Diagnosis and Measurement
B. Nadeau-Dosti
ISBN: 0-79-8669-8
Delay Fault Testing for VLSI Circuits
A. Krstic‚ K-T. Cheng
ISBN: 0-7923-8295-1
Research Perspectives and Case Studies in System Test and Diagnosis
J.W. Sheppard‚W.R. Simpson
ISBN: 0-7923-8263-3
Formal Equivalence Checking and Design Debugging
S.-Y. Huang‚ K.-T. Cheng
ISBN: 0-7923-8184-X
Defect Oriented Testing for CMOS Analog and Digital Circuits
M. Sachdev
ISBN: 0-7923-8083-5
Reasoning in Boolean Networks: Logic Synthesis and Verification
Using Testing Techniques
W. Kunz‚ D. Stoffel
ISBN: 0-7923-9921-8
VERIFICATION BY ERROR MODELING
USING TESTING TECHNIQUES IN HARDWARE VERIFICATION
by
KATARZYNA RADECKA
Concordia University‚ Canada
and
ZELJKO ZILIC
McGill University‚ Canada
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48739-X
Print ISBN: 1-4020-7652-5
©2004 Springer Science + Business Media, Inc.
Print ©2003 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Springer's eBookstore at: http://www.ebooks.kluweronline.com
and the Springer Global Website Online at: http://www.springeronline.com
Dedication
To Maria and our parents
Contents
List of Figures xi
Acknowledgments xv
Chapter 1: Introduction 1
1. DESIGNFLOW 1
2. VERIFICATION – APPROACHES AND PROBLEMS 4
2.1 Verification Approaches 5
2.2 Verification by Simulations 5
2.3 Test Vector Generation 5
2.4 Design Error Models 7
2.5 Other Simulation Methods 9
2.5.1 CoverageVerification 9
2.5.2 Other Metrics 10
2.6 FormalVerification 11
2.7 Model-based Formal Verification Methods 12
2.8 Proof-theoreticalFormalVerification Methods 14
2.9 Spectral Methods in Verification 14
3. BOOKOBJECTIVES 15
Chapter 2: Boolean Function Representations 19
1. BACKGROUND - FUNCTIONREPRESENTATIONS 19
1.1 Truth Tables 20
1.2 Boolean Equations - Sum of Products 21
1.3 Satisfiability of BooleanFunctions 23
1.3.1 Algorithms for SolvingSatisfiability 24
1.4 Shannon Expansion 28
1.5 Polynomial Representation 28
2. DECISIONDIAGRAMS 30
viii Verification by error modeling
2.1 Reduced Ordered Binary Decision Diagrams 31
2.2 Word-Level Decision Diagrams 33
2.2.1 Binary Moment Diagrams 33
2.2.2 Limitations of WLDDs 35
3. SPECTRALREPRESENTATIONS 38
3.1 Walsh-Hadamard Transform 39
3.2 Walsh Transform Variations 40
3.3 Walsh-Hadamard Transform as Fourier Transform 41
4. ARITHMETICTRANSFORM 44
4.1 Calculation of Arithmetic Transform 47
4.1.1 Fast Arithmetic Transform 47
4.1.2 BooleanLattice and AT Calculation 48
4.2 AT and Word-Level Decision Diagrams 49
Chapter 3: Don’t Cares and Their Calculation 51
1. INCOMPLETELY SPECIFIED BOOLEAN FUNCTIONS 51
1.1 Don’t Cares in Logic Synthesis 51
1.2 Don’t Cares in Testing for Manufacturing Faults 52
1.3 Don’t Cares in Circuit Verification 54
2. USINGDON’TCARES FOR REDUNDANCYIDENTIFICATION 55
2.1 Basic Definitions 56
2.2 Calculation of All Don’t Care Conditions 57
2.2.1 Computation of Controllability Don’t Cares 57
2.2.2 Algorithms for Determining CDCs 59
2.3 Algorithms for Computing ODCs 65
2.4 Approximations to Observability Don’t Cares - CODCs 67
Chapter 4: Testing 71
1. INTRODUCTION 71
2. FAULT LIST REDUCTION 73
3. OVERVIEW OF SIMULATORS 73
3.1 True-Value Simulator Types 74
3.2 Logic Simulators 75
4. FAULTSIMULATORS 79
4.1 RandomSimulations 81
4.1.1 Linear Feedback Shift Registers 82
4.1.2 Other Pseudo-Random Test Pattern Generators 88
4.1.3 Final remarks 93
5. DETERMINISTICVECTORGENERATION – ATPG 94
5.1 Deterministic Phase 94
5.2 Search for Vectors 98
5.3 Fault Diagnosis 100
6. CONCLUSIONS 101
Verification by error modeling ix
Chapter 5:Design Error Models 103
1. INTRODUCTION 103
2. DESIGNERRORS 105
3. EXPLICITDESIGNERRORMODELS 107
3.1 Detecting Explicit Errors 110
3.1.1 Application of Stuck-at-value Vector Set 110
3.1.2 Detection of Gate Replacements 110
3.1.3 Universal Test Set Approach 111
4. IMPLICITERRORMODELPRECURSORS 112
4.1 Rationale for Implicit Models 113
4.2 Related Work – Error Models 114
4.2.1 Port Fault Models 114
5. ADDITIVEIMPLICITERRORMODEL 115
5.1 Arithmetic Transform of Basic Design Errors 117
6. DESIGNERRORDETECTION AND CORRECTION 123
6.1 Path Trace Procedure 125
6.2 Back-propagation 126
6.3 Boolean Difference Approximation by Simulations 127
7. CONCLUSIONS 128
Chapter 6:Design Verification by AT 129
1. INTRODUCTION 129
2. DETECTINGSMALLATERRORS 132
2.1 Universal Test Set 132
2.2 AT-based Universal Diagnosis Set 133
3. BOUNDINGERROR BY WALSHTRANSFORM 135
3.1 Spectrum Comparison 137
3.2 Spectrum Distribution and Partial Spectra Comparison 138
3.3 Absolute Value Comparison 140
4. EXPERIMENTALRESULTS 142
4.1.1 Improvements - Neighborhood Subspace Points 145
5. CONCLUSIONS 146
Chapter 7: Identifying redundant gate and wire replacements 147
1. INTRODUCTION 147
2. GATE REPLACEMENT FAULTS 149
2.1 Redundant Replacement Faults 150
2.1.1 Overview of the Proposed Approach 151
3. REDUNDANCYDETECTION BY DON’TCARES 151
3.1 Using Local Don’t Cares 152
3.2 Using Testing - Single Minterm Approximation 154
3.3 RedundantSingleCube Replacements 159
3.3.1 Use of SAT in Redundancy Identification 160
x Verification by error modeling
3.3.2 Passing Proximity Information to SAT 161
4. EXACTREDUNDANTFAULTIDENTIFICATION 163
4.1.1 Preprocessing 164
5. IDENTIFYINGREDUNDANTWIREREPLACEMENTS 164
5.1 Wire Replacement Faults and Rewiring 166
5.2 Detection by Don’t Cares 167
5.3 Don’t Care Approximations 169
5.4 SAT for Redundant Wire Identification 170
5.4.1 Approximate Redundancy Identification 171
6. EXACTWIREREDUNDANCYIDENTIFICATION 172
7. I/OPORTREPLACEMENTDETECTION 175
7.1 Detection of I/O Port Wire Switching Errors 175
8. EXPERIMENTALRESULTS 177
8.1 Gate Replacement Experiments 177
8.1.1 Minimum Distance Replacements 177
8.2 Wire Replacement Experiments 182
8.2.1 True Fan-in Acyclic Replacements 184
8.3 SAT vs. ATPG 185
9. CONCLUSIONS 185
Chapter 8: Conclusions and future work 187
1. CONCLUSIONS 187
2. FUTURE WORK 189
Appendices 191
References 197
Index 211
List of Figures
Figure 1:Design Flow Overview 2
Figure 2:Breakdown of the Design and Verification Efforts 3
Figure 3:Equivalence Checking Paths 12
Figure 4:Distribution of Cases Verified by Simulations and Model Checking
13
Figure 5: Fault Distribution over Time 16
Figure 6:Verification Flow in Our Simulation-based Method 16
Figure 7: Relation Between Minterm and Cube Representations 23
Figure 8:Non-chronological Backtracking Example 27
Figure 9: Multiplexor Representation of Shannon Expansion in Variable 28
Figure 10: BDT for Output of 2-bit Multiplier and Variable Order
31
Figure 11: *BMD of a 2-bit Multiplier 35
Figure 12: Execution of Pascal Triangle Computation 37
Figure 13: Limitations in Representing Complex Multiplication by *BMDs
and BDDs. a) Construction of WLDDs. b) Construction of BDDs 38
Figure 14:Transform Operation 39
Figure 15: Butterfly Diagram for Fast Arithmetic Transform 47
Figure 16: Lattice Structure with Incorporated AT of a 2-Bit Adder 48
Figure 17: Comparing Graph-based Function Representations in Functional
and Spectral Domains 50
Figure 18:A s-a-0 fault at line y 53
Figure 19: Example of a Redundant s-a-1 Fault 53
Figure 20:Example of a Don’t Care Location in a Circuit 55
Figure 21:ODC Computation 56
Figure 22:Example of Sub-circuit S1 and its Environment C 57
