Table Of ContentVariation Tolerant On-Chip Interconnects
ANALOGCIRCUITSANDSIGNALPROCESSING
SeriesEditors:
MohammedIsmail.TheOhioStateUniversity
MohamadSawan.E´colePolytechniquedeMontre´al
Forfurthervolumes:
http://www.springer.com/series/7381
Ethiopia Enideg Nigussie
Variation Tolerant On-Chip
Interconnects
123
EthiopiaEnidegNigussie
UniversityofTurku
Turku
Finland
ethnig@utu.fi
ISBN978-1-4614-0130-8 e-ISBN978-1-4614-0131-5
DOI10.1007/978-1-4614-0131-5
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Preface
The design paradigm shift from single-core to multicore systems and from core-
centric to interconnect-centric designs has emphasized the importance of high
performanceand reliable on-chipinterconnects.In sub-100nm technologies,vari-
abilityhasbecomeamajorchallengeanditisconsideredoneoftheprimarylimiters
fortechnologyscaling.Theinabilitytopreciselycontrolthemanufacturingprocess
leadsto unpredictabledeviceand wire characteristics, whichin turn cause perfor-
mance and power variability besides error-prone behavior. The performance and
reliabilityofaninterconnectisalsoaffectedbytheenvironmentinwhichitoperates
suchastemperature,powersupplyvoltageandnoise.Allthesevariationscausethe
signal propagationdelay of the interconnectto be uncertain which in turn affects
the performance and reliability of the communication significantly. Traditionally
corner based analysis has been used to guard against yield loss resulting from
these variations; however, with increasing number of sources of variation, corner
based methods are becoming overly pessimistic and computationally expensive.
Self-timed design methodologies can make the communication resilient to delay
variations.Morespecifically,self-timeddelay-insensitivelinkscanoperatecorrectly
inthepresenceofdelayvariationsingatesandinterconnectingwires.
In this monograph designs of high performance and variation tolerant on-chip
interconnectsarepresented.Thedesignandimplementationoftheseinterconnects
arebasedonformulationandintegrationofdifferentcircuitleveltechniques.Since
delay variations are inevitable, the design focuses on self-timed delay-insensitive
communication. In this regard, design and optimization of delay-insensitive data
encoding/decoding schemes as well as formulation of efficient communication
protocols are performed. To compensate the delay overhead of delay-insensitive
communication,high speed signaling techniquesare developedand implemented.
Inaddition,a novelhighspeedcompletiondetectiontechniqueisdevisedandim-
plementedtosolvetheperformancebottleneckcausedbyconventionalcompletion
detection methods. A high-throughput and power efficient serial interconnect is
also designed in order to be used as a long-range on-chip communication link.
Furthermore,an interconnectcalibration techniqueafter every powerstart-up of a
systemisdevelopedandimplementedtoensuresignalintegrityoftheinterconnects
v
vi Preface
despiteprocess,wearoutandagingcausedvariations.Aruntimesupplyvoltageand
temperature (VT) variation tolerance technique is also devised and implemented
for the interconnects. These Process, Voltage and Temperature (PVT) variation
tolerance schemes make the interconnects adaptive to the effect of variations,
enablingcontinuousandreliableoperationoftheinterconnect.
The manuscript is organized as follows. The introduction in Chap.1 focuses
on the drive for interconnect-centric design and challenges of global on-chip
communication.InChap.2,thedesigntechniquesusedtoimplementthepresented
highperformancedelay-insensitiveinterconnectsarediscussed.Methodsandbasis
for estimating wire parasitics along with the electrical level modeling of wires is
discussed in Chap.3. Design and analysis of the three delay-insensitive current
sensing on-chip interconnects are presented in Chap.4. In addition, analysis of
theirperformanceandpowerconsumptionaswellascomparisonwithconventional
delay-insensitive on-chip interconnects are presented. In Chap.6, a high speed
completiondetectiontechniqueaswellasitsdesignispresentedinordertoenhance
the performance of the delay-insensitive interconnects. Furthermore, two of the
interconnects presented in Chap.4 are redesigned and presented as case studies
to demonstrate the advantage of the presented completion detection technique.
Analysisoftheirperformance,energydissipationandareabesidescomparisonwith
the referencecases are also discussed. In Chap.6, implementationand analysisof
high-throughputserialon-chipinterconnecttargetedforlong-rangecommunication
is presented. Also, comparison of throughput, energy and area between fully
bit-parallel, bit-serial and semi-serial links are performed. All the interconnects
which are presented in Chaps.4–6are redesignedusing 65nm CMOS technology
and their performance, energy dissipation, and area are compared in Chap.7. In
Chap.8, circuit techniques as well as implementations to tolerate process, supply
VTvariationeffectsonthesignalintegrityoftheinterconnectsarepresented.
Althoughmuchcarehasbeenmadein thepreparationofthe manuscript,flaws
anderrorsmightstillexistduetoerringhumannature.Suggestionsandappropriate
commentsarehighlyappreciated.
Turku,Finland EthiopiaEnidegNigussie
Acknowledgements
Iwouldliketotakethisopportunitytoexpressmysinceregratitudetothepeopleand
institutionsthathavehelpedmetoaccomplishthisresearchwork.Thismanuscript
is developed from my doctoral dissertation and due to this I am grateful to my
doctoral research supervisors Adj. Prof. Juha Plosila, Prof. Jouni Isoaho, and
Prof.HannuTenhunen.Theirinspiration,guidanceandsupporthasbeenthe main
driving force for this research. The support from the Department of Information
Technology, University of Turku, Finland where I carried out this research is
gratefullyacknowledged.
MyheartfeltappreciationgoestoProfessorMohammedIsmail,theserieseditor
ofAnalogCircuitsandSignalProcessing,forhiscommentsonthecontentsofthe
manuscriptaswellasforinvitingmetowritethismonograph.
Many thanks to the editorial staff of Springer, especially Charles B. Glaser,
Senior Editor–Electrical Engineering, they have been wonderfully supportive and
encouraging.
A large dept of gratitude is owed to my wonderful mother Yisgedu Agonafir.
ThoughIlostyoumanyyearsago,youarestillinspiringmetoworkhardandreach
further.
vii
Contents
1 Introduction .................................................................. 1
1.1 EmergenceofInterconnect-CentricDesign............................ 1
1.1.1 DeviceandInterconnectScaling............................... 2
1.1.2 System-on-ChipandMulticoreSystems ...................... 3
1.1.3 Network-on-Chip............................................... 4
1.2 ChallengesofGlobalOn-ChipInterconnect........................... 5
1.2.1 PerformanceandPowerConsumption......................... 5
1.2.2 VariabilityandReliability...................................... 6
1.3 GlobalOn-ChipCommunicationTechniques ......................... 7
1.3.1 GALSCommunication......................................... 8
1.3.2 Self-timedDelay-InsensitiveCommunication ................ 8
1.4 RelatedWork............................................................ 9
1.4.1 HighPerformanceInterconnect................................ 9
1.4.2 VariationTolerantInterconnect ................................ 10
1.4.3 HighPerformanceandVariationTolerantInterconnect....... 10
2 InterconnectDesignTechniques............................................ 11
2.1 HandshakingProtocols ................................................. 11
2.2 DataEncodingTechniques ............................................. 14
2.3 DataDecodingTechniques............................................. 16
2.4 CompletionDetectionTechniques ..................................... 17
2.5 Self-timedComponents................................................. 17
2.6 On-ChipSignalingSchemes............................................ 18
2.6.1 Current-ModeandCurrentSensingSignaling ................ 19
2.6.2 Voltage-ModeSignaling:Reference........................... 22
2.7 ChapterSummary....................................................... 23
3 On-ChipWireModeling .................................................... 25
3.1 WireParasiticEstimationandExtraction.............................. 25
3.1.1 Resistance....................................................... 26
3.1.2 Capacitance ..................................................... 28
3.1.3 Inductance....................................................... 29
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x Contents
3.2 ElectricalLevelWireModeling........................................ 31
3.3 ChapterSummary....................................................... 33
4 DesignofDelay-InsensitiveCurrentSensingInterconnects............. 35
4.1 Level-EncodedDual-RailCurrentSensingInterconnect.............. 36
4.1.1 DataEncoderandDriver....................................... 38
4.1.2 Receiver,DecoderandCompletionDetector.................. 38
4.1.3 AcknowledgmentTransmission................................ 39
4.1.4 SimulationResultsandAnalysis............................... 40
4.1.5 EffectofCrosstalkonTiming.................................. 43
4.2 1-of-4EncodedCurrentSensingInterconnect......................... 45
4.2.1 EncoderandDriver............................................. 48
4.2.2 Receiver......................................................... 49
4.2.3 DecoderandCompletionDetector............................. 50
4.2.4 AcknowledgmentTransmission................................ 51
4.2.5 ReferenceVoltage-ModeInterconnects ....................... 52
4.2.6 SimulationResultsandAnalysis............................... 53
4.3 Dual-RailEncodedDifferentialCurrentSensingInterconnect....... 59
4.3.1 EncodingandItsImplementation.............................. 59
4.3.2 Driver,ReceiverandCompletionDetector.................... 62
4.3.3 AcknowledgmentTransmission................................ 64
4.3.4 SimulationResultsandAnalysis............................... 65
4.4 ChapterSummary....................................................... 69
5 EnhancingCompletionDetectionPerformance.......................... 71
5.1 Delay-InsensitiveBitParallelTransmission........................... 71
5.2 High-SpeedCompletionDetectionTechnique ........................ 75
5.3 CaseStudies............................................................. 77
5.3.1 1-of-4EncodedCurrentSensingInterconnect ................ 77
5.3.2 Dual-railEncodedDifferentialCurrent
SensingInterconnect............................................ 78
5.3.3 AcknowledgmentTransmission................................ 80
5.4 ReferenceCases......................................................... 81
5.5 SimulationResultsandAnalysis....................................... 82
5.5.1 WireModel ..................................................... 82
5.5.2 SimulationsSetup............................................... 82
5.5.3 PerformanceAnalysis .......................................... 83
5.5.4 PowerAnalysis ................................................. 85
5.5.5 NoiseAnalysis.................................................. 88
5.5.6 Post-LayoutSimulation ........................................ 89
5.5.7 AreaComparison............................................... 89
5.6 ChapterSummary....................................................... 91
6 EnergyEfficientSemi-SerialInterconnect................................ 93
6.1 Long-RangeLinkinNoC............................................... 95
6.2 High-ThroughputSerialOn-ChipInterconnect........................ 98
6.2.1 CommunicationProtocol....................................... 98
