UNIVERSITY OF CALIFORNIA Los Angeles Crossbar Arbitration in Interconnection Networks for ...

213 Pages·2007·1.69 MB·English

UNIVERSITYOFCALIFORNIA
LosAngeles
CrossbarArbitration in Interconnection Networks
for Multiprocessors and Multicomputers
Adissertation submitted in partial satisfaction of the
requirements for the degree Doctor of Philosophy
in Computer Science
by
Hsin-ChouChi
1994
! Copyright by
Hsin-ChouChi
1994

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i
To my parents,
for their love and understanding.
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Table of Contents
Chapter One - Introduction ........................................................................... 1
1.1. CrossbarArbitration ............................................................................ 5
1.2. Organization of the Dissertation .......................................................... 8
Chapter Two - Previous Work ...................................................................... 11
2.1. Arbitration Problems in Computer Systems ........................................ 11
2.1.1. Conventional BusArbitration ................................................... 12
2.1.2. Multiple BusArbitration ........................................................... 14
2.1.3. Segmented Ring BusArbitration .............................................. 16
2.2. Buffered Communication Switches ..................................................... 18
2.2.1. Performance Impact of Switch Buffers ..................................... 19
2.2.2. Communication Switch Designs ............................................... 21
2.3. The ComCoBB Project ........................................................................ 25
2.3.1. High-Performance Multi-Queue Buffers .................................. 26
2.3.2. Supportfor High-Priority Traffic .............................................. 29
2.3.3. Dynamic Virtual Circuits .......................................................... 32
Chapter Three - Symmetric Crossbar Arbiters ........................................ 38
3.1. Symmetric CrossbarArbitration .......................................................... 39
3.2. Symmetric CrossbarArbiters .............................................................. 43
3.2.1. The Importance of the Arbitration Scheme .............................. 44
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3.2.2. The Skewed Two-Step Arbiter ................................................. 49
3.2.3. The Wave FrontArbiter ............................................................ 50
3.2.4. The Wrapped Wave FrontArbiter ............................................ 52
3.3. Performance Evaluation ...................................................................... 54
3.3.1. Simple Probabilistic Analysisfor a 2×2Switch ....................... 54
3.3.2. Probabilistic Analysisfor an n×nSwitch .................................. 56
3.3.3. Simulation of SynchronousNetworks ...................................... 65
3.3.3.1. Performance Measurement .......................................... 65
3.3.3.2. Performance Evaluation of a 4×4Switch .................... 69
3.3.3.3. Performance Evaluation of a 64×64Network ............. 71
3.3.3.4. Impact of Buffer Size and Switch Size ....................... 73
3.3.4. Simulation of AsynchronousNetworks .................................... 77
3.4. Implementation .................................................................................... 85
3.4.1. Logic and Circuit Design .......................................................... 86
3.4.2. VLSILayout and Circuit Simulation ........................................ 88
3.5. Summary and Conclusions .................................................................. 91
Chapter Four - Decomposed Arbiters for Large Crossbars ................... 95
4.1. Performance Impact of Large Crossbars ............................................. 97
4.2. Decomposed Arbitration for Large Crossbars ..................................... 101
4.3. Performance Evaluation ...................................................................... 110
4.4. Design of Decomposed Arbiters .......................................................... 118
4.5. Reducing the Number of Queues ......................................................... 125
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4.6. Summary and Conclusions .................................................................. 129
Chapter Five - Starvation Prevention .......................................................... 131
5.1. Starvation Prevention for CrossbarArbitration ................................... 132
5.1.1. Starvation Prevention in SynchronousNetworks ..................... 132
5.1.2. Starvation Prevention in AsynchronousNetworks ................... 135
5.2. Performance Evaluation ...................................................................... 138
5.2.1. Uniform Traffic ......................................................................... 139
5.2.2. Nonuniform Traffic ................................................................... 144
5.2.2.1. Simulations for a 4×4Switch ...................................... 145
5.2.2.2. Simulations for a 16×16Network ............................... 154
5.3. Implementation .................................................................................... 160
5.4. Summary and Conclusions .................................................................. 165
Chapter Six - Arbiter Support for Adaptive Routing and
for High-Priority Traffic ....................................................... 166
6.1. Arbiter Design Supporting Adaptive Routing ..................................... 166
6.2. Arbiter Design Supporting High-Priority Traffic ................................ 173
Chapter Seven - Summary ............................................................................. 181
Bibliography ....................................................................................................... 185
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List of Figures
1.1 AnIndirect Network for Multiprocessors ............................................. 2
1.2 ADirect Network for Multicomputers ................................................. 2
1.3 Organization of a Typical Communication Switch .............................. 3
1.4 ASwitch with FIFOInput Buffers ....................................................... 5
1.5 ASwitch with Multi-Queue Input Buffers ........................................... 7
1.6 ASwitch with DAMQInput Buffers .................................................... 7
2.1 AShared-Bus Multiprocessor ............................................................... 12
2.2 AUser-Resource Model of Shared BusArbitration ............................. 13
2.3 AMultiple-Bus Multiprocessor ............................................................ 15
2.4 AUser-Resource Model of Multiple BusArbitration .......................... 16
2.5 AMultiprocessor Based onthe Segmented Ring Bus .......................... 17
2.6 AUser-Resource Model of Segmented Ring BusArbitration ............. 18
2.7 Two Different Buffer Designs .............................................................. 20
2.8 FourAlternative Buffer Designsfor Communication Switches .......... 28
2.9 AVirtual Circuit ................................................................................... 34
2.10 AMulticomputer Node ....................................................................... 37
3.1 Switches with FIFOBuffers and DAMQBuffers ................................ 40
3.2 ACrossbarArbiter in Context .............................................................. 41
3.3 AUser-Resource Model of Symmetric CrossbarArbitration .............. 42
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