Universit`a degli Studi di Pavia A/D Converters in Submicron CMOS Technology

177 Pages·2008·2.86 MB·English

Universita` degli Studi di Pavia
Facolta` di Ingegneria
Dottorato di ricerca in ingegneria elettronica,
informatica ed elettrica
XXI ciclo
A/D Converters in Submicron
CMOS Technology
Tutor:
Chiar.mo Prof. Piero Malcovati
Co-Tutor:
Chiar.mo Prof. Andrea Baschirotto
Coordinatore del Corso di Dottorato:
Chiar.mo Prof. Giuseppe Conciauro
Tesi di Dottorato
di Luca Picolli
Allo Zio Pentagramma
Contents
Introduction 1
1 The A/D Conversion 9
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Anti-Aliasing Filtering and Sampling . . . . . . . . . . . . . . 10
1.2.1 Sampling Jitter . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 kT/C Noise . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 A/D Converter Topologies 23
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.1 Types of ADCs . . . . . . . . . . . . . . . . . . . . . . 24
2.2.2 General Features . . . . . . . . . . . . . . . . . . . . . 24
2.2.3 Static Specifications . . . . . . . . . . . . . . . . . . . 25
2.2.4 Dynamic Specification . . . . . . . . . . . . . . . . . . 27
2.3 Full-Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.1 Comparators . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4 Pipeline ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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2.4.1 1.5b Stage . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5 Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . 34
2.5.1 Delta and Sigma-Delta Modulation . . . . . . . . . . . 35
2.6 Time Interleaved ADC . . . . . . . . . . . . . . . . . . . . . . 38
2.6.1 Offset Mismatch Effects . . . . . . . . . . . . . . . . . 38
2.6.2 Gain Mismatch Effects . . . . . . . . . . . . . . . . . . 39
2.6.3 Timing Errors . . . . . . . . . . . . . . . . . . . . . . . 40
3 Clock-Less Pipeline-Like ADC 41
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5 2b Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6 1.5b Stage Simulations . . . . . . . . . . . . . . . . . . . . . . 54
3.6.1 Conversion Speed and Architecture Limits . . . . . . . 55
3.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 56
3.7.1 Layout Issues . . . . . . . . . . . . . . . . . . . . . . . 57
3.7.2 Measured Performance . . . . . . . . . . . . . . . . . . 58
3.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 120MHz-250MHz 8b Pipeline ADC 63
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1.1 Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . 64
4.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3 S&H Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4 2.5b Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.4.1 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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4.4.2 2.5b Flash ADC . . . . . . . . . . . . . . . . . . . . . . 73
4.5 2b Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 75
4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5 1.6GHz 52dB SNDR Pipeline ADC 83
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.2.1 Single-Path ADC Structure . . . . . . . . . . . . . . . 86
5.3 3.5b Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.1 3.5b Flash ADC . . . . . . . . . . . . . . . . . . . . . . 91
5.3.2 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.3 MDAC Operational Amplifier . . . . . . . . . . . . . . 96
5.4 1.5b Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.5 2.5b Stage with Operational Amplifier Sharing . . . . . . . . . 99
5.6 4b Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.7 Reference Voltage Buffer . . . . . . . . . . . . . . . . . . . . . 101
5.8 Clock Tree and Digital Blocks . . . . . . . . . . . . . . . . . . 103
5.9 Simulations Results . . . . . . . . . . . . . . . . . . . . . . . . 105
5.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6 Σ∆ Modulator for MEMS Microphones 109
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . 111
6.3 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.4 Σ∆ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.4.1 Second-Order, Multi-Bit, Analog Σ∆ Modulator . . . . 115
6.4.2 Switched-Capacitor Implementation . . . . . . . . . . . 117
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6.4.3 Integrators and Adder . . . . . . . . . . . . . . . . . . 117
6.4.4 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . 121
6.4.5 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.4.6 Fourth-Order, Single-Bit, Digital Σ∆ Modulator . . . . 124
6.5 Simulations Results . . . . . . . . . . . . . . . . . . . . . . . . 127
6.6 Conlcusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Conclusions 131
A Verilog Code 135
B SD Toolbox Procedure 139
Acknowledgments 165
Bibliography 167
iv
Introduction
Analog-to-digital (A/D) converters (ADCs) are key blocks in modern micro-
electronic systems. With the fast improvement of CMOS fabrication tech-
nology, more and more signal-processing functions are implemented in the
digital domain for lower cost, lower power consumption, higher yield, and
higher re-configurability. This has recently generated a great demand for
low-power, low-voltage ADCs that can be realized in a mainstream deep-
sub-micron CMOS technology.
ThethesisfocusesonthedesignofpipelineADCswhicharethemostused
in systems in which medium resolution or/and wide bandwidth or/and high
sampling rates are required. The resolution and sampling rate of pipeline
ADCs cover a wide range of applications, including CCD imaging, ultrasonic
medical imaging, digital receivers, base stations, digital video (for example,
HDTV), xDSL, cable modems, and fast Ethernet. Applications with lower
sampling rates are still the domain of the successive approximation register
(SAR) and oversampling/sigma-delta ADCs. The highest sampling rates (a
few hundred MS/s or higher) are typically obtained using flash ADCs (low
resolution) or time-interleaved structures (high resolution).
Before illustrating the content of this thesis it is useful to provide a brief
comparison between pipeline ADC and the other ADC architectures. A
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INTRODUCTION
pipelineADCisbasicallyamulti-stepquantizerinwhichaseriesofsimilaror
identical stages, which are low-resolution A/D and D/A converters, provide
the digitization of the analog input signal. The main features of the pipeline
ADC architecture are:
• medium resolution (10-12 bits);
• high sampling rate, up to a few hundreds MS/s;
• wide input bandwidth, usually half of the sampling rate;
• latency value depending on the number of the stages.
Pipeline versus SAR ADC – In a successive approximation register
(SAR) ADC, the output digital word is determined by a single, high-speed,
high-accuracy comparator, bit by bit, from the most-significant bit (MSB)
downtotheleast-significantbit(LSB).ThisserialnatureofSARADCslimits
their operating speed to no more than a few MS/s, and event less for high
resolutions (14 to 16 bits). A pipeline ADC, by contrast, employs a parallel
structure, inwhicheachstageworksononeorfewbits(ofsuccessivesamples)
atthesametime. AlthoughthereisonlyonecomparatorinaSARADC,this
comparator must be fast (clocked at approximately the number of bits times
the sample rate) and as accurate as the ADC itself. By contrast, none of the
comparators inside a pipeline ADC needs this degree of speed or accuracy. A
pipelineADC,however, generallyrequiressignificantlymoresiliconareathan
an equivalent SAR ADC. A SAR ADC also features a latency of only one
cycle (one cycle = 1/F , F being the sampling frequency), while a pipeline
s s
ADC shows a latency of n sampling period, where n is the number of pipeline
stages. Both pipeline and SAR ADCs with more than 12 bits of resolution
usually require some form of trimming or calibration.
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INTRODUCTION
Pipeline versus Flash ADC – A pipeline ADC requires accurate ana-
log amplification in the interstage amplifiers, and thus significantly linear
settling. A purely flash ADC, by contrast, includes a large bank of compara-
tors, each consisting of wide-band, low-gain pre-amplification stage, followed
by a latch. The pre-amplification stages, unlike amplifiers in a pipeline ADC,
must provide a gain nor linear nor accurate; only the comparator decision
pointsmustbeaccurate. Asaresult, apipelineADCcannotmatchthespeed
of a flash ADC. Extremely fast 8b flash ADCs (or their folding/interpolation
variants) do exist with sampling rates as high as 1.5GS/s. It is much harder
to find a 10b flash ADC, while 12b (or above) flash ADCs are not feasible
because in a flash ADC the number of comparators increases exponentially
with the number of bits. Simultaneously, each comparator must be twice
as accurate. In a pipeline ADC, by contrast, the complexity only increases
approximately linearly with the resolution.
Pipeline ADC versus Sigma-Delta Modulator–Traditionally, over-
sampling sigma-delta (Σ∆) converters have been used in digital audio sys-
tems, featuring a limited bandwidth (about 22kHz). Some Σ∆ converters
can reach a bandwidth of 1MHz to 2MHz, much lower than the bandwidth
achievable with a pipeline ADC, with 12 to 16 bits of resolution. These
specifications require high-order Σ∆ modulators (for example, fourth-order
or even higher), incorporating a multi-bit ADC and multi-bit feedback DAC.
Their main applications are in ADSL. A Σ∆ converter needs no special trim-
ming nor calibration, even for 16 to 18 bits of resolution. They also require
non aggressive anti-aliasing filters at the analog inputs, because the sampling
rate is much higher than the effective bandwidth. The back-end digital filters
take care of filtering the out-of-band spectrum. Σ∆ converters trade speed
for resolution. The need to sample many times (for example, at least 16
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INTRODUCTION
Figure 1: A/D converter topologies as a function of resolution and sampling
rate
times, but often much more) to produce one final sample, causes the internal
analog components in the Σ∆ modulator to operate much faster than the
final data rate. The digital decimation filter is also nontrivial to design, and
consumes a lot of silicon area. The fastest, high-resolution Σ∆ converters
do not have more than a few MHz of input signal bandwidth. Like pipeline
ADCs, Σ∆ converters also have latency.
In view of the above considerations, pipeline ADCs are the choice for
sampling rates from a few MS/s up to a few hundreds of MS/s. Design com-
plexity increases only linearly (not exponentially) with the number of bits,
thus providing converters with high speed, high resolution, and low power
consumption at the same time. Pipeline ADCs are very useful for a wide
range of applications, most notably in digital communication where the ADC
dynamic performance is often more important than traditional DC specifi-
cations, like differential nonlinearity (DNL) and integral nonlinearity (INL).
The data latency of pipelined ADCs is of little concern in most applications.
Figure 1 shows the state of art of ADCs.
4