Understanding Serial LVDS Capture in High-Speed ADCs

33 Pages·2013·1.56 MB·English

Understanding Serial LVDS Capture in
High-Speed ADCs
Application Report
LiteratureNumber:SBAA205
July2013
Contents
Preface ....................................................................................................................................... 4
1 Introduction ........................................................................................................................ 5
2 CapturingDatafromaSerialLVDSInterface:Ideal Case ......................................................... 7
3 ReceiverCaptureSchemes ................................................................................................. 10
3.1 LatchingSerializedADCDataBitsintotheS2PShiftRegister ..................................................... 10
3.1.1 UsingDelayElements ........................................................................................... 10
3.1.2 UsingPLLs ........................................................................................................ 11
3.1.3 PLLClockEdgeSelectionLogic ............................................................................... 12
3.1.4 DeterminationofCorrectData .................................................................................. 12
3.2 AligningParallelOutputDatafromtheS2PShiftRegister .......................................................... 13
3.2.1 DeterminingifCapturedDataareAlignedCorrectly ......................................................... 16
3.2.2 FrameAlignmentLogicUsingSYNCPattern................................................................. 18
4 SummaryofCaptureSchemes ............................................................................................ 19
5 UnderstandingADCInterfaceTimingSpecifications .............................................................. 22
6 AchievingTimingClosureintheSystem .............................................................................. 25
6.1 ActualSetupTime ......................................................................................................... 26
6.2 ActualHoldTime .......................................................................................................... 27
6.3 PCBSkew .................................................................................................................. 28
7 UnderstandingSourceSynchronous Interface ...................................................................... 29
2 Contents SBAA205–July2013
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List of Figures
1-1. LVDSOutputTimingDiagram............................................................................................. 5
1-2. TypicalMultichannelADCwithaSerialLVDSInterface............................................................... 6
2-1. CapturingSerialLVDSData:SimplestScheme........................................................................ 7
2-2. DoubleDataRateIO....................................................................................................... 8
2-3. DDRIOTiming.............................................................................................................. 8
3-1. UsingVariableDelaysinanFPGA ..................................................................................... 10
3-2. PLLsinanFPGAwithMulti-PhaseOutputs........................................................................... 11
3-3. MultiplePhaseClocksatthePLLOutput.............................................................................. 11
3-4. DataCapturedwithVariousClockEdges.............................................................................. 12
3-5. DataAlignmentwithFrameClock:IdealCase........................................................................ 13
3-6. DataMisalignmentResultingfromaDelayedFrameClock......................................................... 14
3-7. DataMisalignmentResultingfromanAdvancedFrameClock...................................................... 15
3-8. UsingtheSYNCTestPatterntoDetermineDataMisalignment:DelayedFrameClock......................... 16
3-9. UsingtheSYNCTestPatterntoDetermineDataMisalignment:AdvancedFrameClock...................... 17
3-10. OverallFrameAlignmentScheme...................................................................................... 18
4-1. CaptureSchemeUsingPLL:One-WireInterface..................................................................... 19
4-2. CaptureSchemeUsingDelays:One-WireInterface ................................................................. 19
4-3. CaptureSchemeforTwo-WireInterface............................................................................... 20
4-4. CaptureSchemeforMultipleADCDevicesusingPLLs ............................................................. 21
4-5. CaptureSchemeforMultipleADCDevicesusingDelays........................................................... 21
5-1. SetupTimeDefinition..................................................................................................... 22
5-2. HoldTimeDefinition....................................................................................................... 23
5-3. DataValidTimeDefinition................................................................................................ 23
5-4. SkewAmongLVDSOutputsoftheADC............................................................................... 24
6-1. TimingAnalysis............................................................................................................ 25
6-2. ActualSetupTime......................................................................................................... 26
6-3. ActualHoldTime.......................................................................................................... 27
7-1. JitterSource................................................................................................................ 29
7-2. JitterinDataandClockPaths........................................................................................... 30
7-3. EyeUsinganInternalBitClock(Case1)andExternalBitClock(Case2)........................................ 31
7-4. JitterinDataandClockPathsComparedwithanExternalorIdealClock........................................ 32
SBAA205–July2013 ListofFigures 3
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Preface
SBAA205–July2013
Abstract
Vinod Paliakara, Shantanu Prabhudesai...................................... High-Performance Analog Products
This application note describes various schemes of interfacing serialized low-voltage differential signaling
(LVDS) data outputs from high-speed analog-to-digital converters (ADCs) to a field-programmable gate
arrays (FPGAs) or other application-specific integrated circuit (ASIC)-based receivers. This note provides
an introduction to standard one-wire interfaces and other interface variants (such as two-wire). This note
describes in detail the two key points required for reliable data capture: bit clock edge selection and frame
alignment. Schemes for capturing data from multiple ADC devices are also detailed. LVDS timing
parameters, as found in TI data sheets, are explained along with a detailed introduction to jitter in a
source-synchronousinterface.
Alltrademarksarethepropertyoftheirrespectiveowners.
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Chapter 1
SBAA205–July2013
Introduction
Amonghigh-speedADCsoperatingattensofmegahertztohundredsofmegahertz,thepreferred output
datainterfaceisserializedLVDS.ThispreferenceisespeciallytrueinmultichannelADCssuchasTI’s
ADS528x,ADS529x,andADS5263families. TheserializedLVDSinterfaceisalsoseeninanalogfront-
ends(AFEs)thatincludeamultichannelADC,suchastheAFE580xfamilies. Thedifferentialsignaling
protocolofanLVDS pairofferscommon-modenoiserejection,thusenablinghigher datatransmission
speeds(typicallyupto1GbpsperLVDSpair).
Figure1-1showsatypicalserializedLVDSinterfacefor oneADCchanneloperatingonasamplingclock
frequency(f ).Thecharacteristicsofthisinterfaceare:
S
1. ADCdataareoutputseriallyfromD0toDN-1(foranN-bit resolutionADC)ateverysamplingclock
cycle.Thisoutputresultsinaserial datarateof(f ×N)bitspersecond.
S
2. Anassociated50%dutycyclebitclockisoutput with afrequencyof(f ×N/2). Thebitclockis
S
typicallycenter-alignedandbothclockedgescanbeusedtolatchserialADCdata. Therefore,thebit
clockisreferredtoasadoubledatarate(DDR)bit clock.
3. Anassociated50%dutycycleframeclockisoutput with afrequencyoff .Asthenamesuggests,the
S
frameclockrisingedgetransitionsarealignedwiththeframing ADCdatabits(D0andDN-1).This
alignmenthelpsthereceivertocorrectlyloadparalleldataafterde-serialization.Notethat theframe
clockrisingandfallingedgesarealignedwith thetransitionsofdata.
Thisinterfaceisdescribedasaone-wire, LSB-firstinterfacewithN-xserialization.
Input Clock
(CLK Frequency = fS)
Frame Clock
(ADCLK Frequency = 1x fS)
Bit Clock
(LCLK Frequency = 6x fS)
Output Data(1) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10
(OUTA Data rate = 12x fS) (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11) (D0) (D1)
Sample N
Sample N+1
(1) TheupperdatabitistheMSB-firstmodedatabitandthelowerdatabitistheLSB-firstmodedatabit.
Figure1-1.LVDSOutputTimingDiagram
Somevariationsofthisinterfaceinclude:
1. Two-wireinterface:Athighsamplingclockfrequencies, theserialdataratebecomesveryhigh.In
suchcases,theADC dataareoutputseriallyovertwoLVDSpairs.Forexample,bitsD0toD(N/2)-1
areoutputoveroneLVDS pairandtheother bitsD(N/2)toDN-1overthesecondpair.Withhalfthe
numberofbitstransmittedperLVDSpair oneachsamplingclockcycle, theserialdatarateisreduced
to(f ×N/2)bitspersecond.
S
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2. MSB-first:theADCdatabitsareseriallytransmittedfromtheMSBbit(DN-1)totheLSBbit,D0.
AnadvantageoftheserialLVDS interfaceisthesavingsinpin-countresultingfromtheuseofonlytwo
pins(oneLVDS pair)perADCchannel. Therefore,thisinterfaceismost commonlyfoundinmultichannel
ADCdevices.Atypicalmultichanneldevicehasone(or two)LVDSpairsperADCchannel, onecommon
bitclockoutput,andoneframeclockoutput. RefertoFigure1-2for theLVDSoutput interfaceofan 8-
channelADCdevice.
OUT1A_P
IN1P Sampling Digital Processing OUT1A_N
12-BitADC Serializer
IN1N Circuit Block OUT1B_P
OUT1B_N
OUT2A_P
IN2P Sampling Digital Processing OUT2A_N
12-BitADC Serializer
IN2N Circuit Block OUT2B_P
OUT2B_N
OUT3A_P
IN3P Sampling Digital Processing OUT3A_N
12-BitADC Serializer
IN3N Circuit Block OUT3B_P
OUT3B_N
OUT4A_P
IN4P Sampling Digital Processing OUT4A_N
12-BitADC Serializer
IN4N Circuit Block OUT4B_P
OUT4B_N
LCLKP
CLKP LCLKN
CLOCKGEN PLL
CLKN ADCLKP
ADCLKN
SYNC
OUT5A_P
IN5P Sampling Digital Processing OUT5A_N
12-BitADC Serializer
IN5N Circuit Block OUT5B_P
OUT5B_N
OUT6A_P
IN6P Sampling Digital Processing OUT6A_N
12-BitADC Serializer
IN6N Circuit Block OUT6B_P
OUT6B_N
OUT7A_P
IN7P Sampling Digital Processing OUT7A_N
12-BitADC Serializer
IN7N Circuit Block OUT7B_P
OUT7B_N
OUT8A_P
IN8P Sampling Digital Processing OUT8A_N
12-BitADC Serializer
IN8N Circuit Block OUT8B_P
OUT8B_N
Reference Control SDOUT
Interface
Device
Figure1-2.TypicalMultichannelADCwithaSerial LVDSInterface
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Chapter 2
SBAA205–July2013
Capturing Data from a Serial LVDS Interface: Ideal Case
Thesimplestcaptureschemetoreceivedatafromaserialinterfaceconsistsofadoubledatarate (DDR)
logicblockfollowedbyaserial-to-parallelshiftregister, asshowninFigure2-1.Thelengthofthe shift
registerchainmust beatleast(N/2)flip-flops.Ateveryframeclockrisingedge,theparalleldata output
frombothshiftregisterchainsarelatched.Theoutput isaframe-alignedparalleldatawordofN-bits(D0
toDN-1).
D10 D8 D6 D4 D2 D0
Serial DataO InUpTunt D Q Rising D Q D Q D Q D Q D Q D Q
Q Falling
CLK CLK CLK CLK CLK CLK
Bit LCCloLcKk CLKOUT
D11 D9 D7 D5 D3 D1
D Q D Q D Q D Q D Q D Q
CLK CLK CLK CLK CLK CLK
D2 D0
D[11:0] DATA[11:0]
D Q
ADCLK
CLK
Figure2-1.CapturingSerial LVDSData:SimplestScheme
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TheDDR blocklatchesinputserialdataatbothedgesofthebit clockandoutputstwodatastreams: one
correspondingtotherisingedgeofthebit clock(Q rise)andtheother correspondingtothefallingedge of
thebitclock(Qfall,asshowninFigure2-2). Therisingandfallingdatastreamsarethenappliedto the
shiftregister.
Serial Data Input D Q Data Out Rising
OUTn
Bit Clock
LCLK
Data Out Falling
D Q D Q
Data Out Falling Relatched
DDR IO
Output Clock
Figure2-2. DoubleDataRateIO
NotethattheDDRblockre-latchesthedatastreamfallingedgeatthenextbitclockrisingedgeand
outputstherisingandfallingedgedatastreamsattherisingbitclockedge,whichisusedbyallthe flip-
flopsintheshiftregisterchain.Asaresult,dataarevalidfor roughlyhalf abit clockperiodattheDDRIO
input,whereasdataarevalidforalmostonebit clockperiodfor theremainingflopsintheshiftregister
chain.Figure2-3showsaDDRIOtimingdiagram.
Data are valid for approximately
a half bit clock period.
Data are valid for approximately
one bit clock period.
Figure2-3. DDRIO Timing
Thisdifferenceimpliesthatthetimingconstraint for theflip-flopsintheDDRblockaloneiscritical
comparedtotherestoftheflip-flops.
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MostFPGAshaveaDDRflip-flopandregisteraspart ofthelogiclibrary. TheDDRIO elementacceptsa
singleclockandregistersdataattheinputdatapinatbothclockedges.TheDDRIO elementisalso
physicallylocatedclosetotheFPGAreceiver pins,thushelpingminimizeanydelayscausedbyrouting in
theFPGA.Therefore,TI recommendsusingtheDDRIO elementtointerfacetotheADCserialLVDS
interface.
Ideally,thereisnoadditionalskewbetweentheserialLVDSdata, LVDSbitclock, andLVDSframeclock
signalscausedbydelaysinthePCBandFPGAinternalrouting. Inarealsituation,theeffectsoftrace
delaysinthePCBandFPGAroutingcannotbeignored.
Chapter3andChapter4describevariousimplementationsfor capturingdatafromaserializedADC
interfaceinareal-worldsituation.
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Chapter 3
SBAA205–July2013
Receiver Capture Schemes
Anycapturesolutionmust implementtwomajorfunctions:
1. LatchingtheserializedADC databitscorrectlyintotheserial-to-parallel(S2P)shiftregister usingthe
ADCbitclock(serializedclockdomain), and
2. AligningtheparalleloutputdatafromtheS2Pregisterscorrectly(parallelclockdomain).
VariousmethodsofimplementingthesefunctionsarediscussedintheLatchingSerializedADSData Bits
intotheS2P ShiftRegister,AligningParallelOutputDatafromtheS2PShiftRegister,Determiningif
CapturedDataareAlignedCorrectly,andFrameAlignmentLogicUsingSYNCPatternsections.
3.1 Latching Serialized ADC Data Bits into the S2P Shift Register
Asexplainedpreviously,areal-worldapplicationhasdelaysresultingfromPCBtracesandFPGArouting.
Thesedelaysmust betakenintoaccount duringtiminganalysis.Inmanycases(especiallyfor datarates
>600Mbps),meetingthetimingrequirementswith theseeffectscanbedifficult.Forsuchcases,one
commonsolutionisusingadelayedversionoftheADCbitclockfor latchingdataintotheshiftregister.
Thedelaycanbeaccomplishedby:
• Usingdelayelements(externaltotheADCandreceiverORbuiltintothereceiveritself), andby
• Usingphase-lockedloops(PLLs)
3.1.1 Using Delay Elements
Animportantconsiderationwhenusingthisschemeisthedelayvariationacrossprocess, supplyvoltage,
andtemperature.Also,ensurethattimingismet atbothminimum andmaximumdelayvalues. Withthese
considerationsinmind,usingcircuitssuchasdelay-lockedloops(DLLs)ispreferabletogeneratedelays
thatdonotvarywithprocess,supplyvoltage,andtemperature.ManyFPGAshavebuilt-inDLLelements
thatcanbeusedtoprovidedelayswithincertainranges(uptoafewhundredpicoseconds).Figure 3-1
showsadiagramofvariabledelaysusedinanFPGA.
Odd Sample Bit
Serial Data Input
OUTn LVDS IDELAY IDDR
EvenSample Bit
Bit Clock
LVDS IDELAY BUFIO Sample Clock
LCLK
Figure3-1.UsingVariableDelaysinanFPGA
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