Table Of ContentUNDERSTANDING
BEHAVIORAL SYNTHESIS
A Practical Guide to High-Level Design
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UNDERSTANDING
BEHAVIORAL SYNTHESIS
A Practical Guide to High-Level Design
John P. Elliott
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
......
" Library of Congress Cataloging-in-Publication Data
Elliott, John P., 1966-
Understanding behavioral synthesis: a practical guide to high
-level design / John P. Elliott
p. cm.
Includes bibliographical references.
Additional material to this book can be downloaded from http://extras.springer.com.
ISBN 978-1-4613-7300-1 ISBN 978-1-4615-5059-4 (eBook)
DOI 10.1007/978-1-4615-5059-4
1. Digital integrated circuits--Design and construction--Data
processing. 2. System design--Data processing. 3. VHDL (Hardware
description language) 4. Abstraction. I. Title.
TK7874.65.E38 1999
621.3815--dc21 99-27961
CIP
Copyright © 1999 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1999
Softcover reprint of the hardcover 1st edition 1999
Second printing with corrections 2000.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo
copying, recording, or otherwise, without the prior written permission of the
publisher, Springer Science+Business Media, LLC.
Printed on acid-free paper.
Table of Contents
Preface xv
Acknowledgements xvii
1. How Did We Get Here?
Chapter 1 provides a brief history of electronic design automation from IC
mask generation to schematic capture to logic synthesis and finally to
behavioral synthesis. Extreme market pressures and rapid changes in
silicon technology have changed the design process which has in turn led to
thedevelopmentofdesigntools of increasing complexity.
1.1 StepBackInTime 1
1.2 TheYearIs1981... 1
1.3 TheYearIs1986... 2
1.4 TheYearis1991... 3
1.5 Today... 4
2. An Introduction to Behavioral Synthesis
Chapter2 introduces the behavioral design process. The ability to evaluate
multiple architectures (which may not be practical in traditional system
design) isan importantadvantageofthe behavioral design process.
2.1 WhyBehavioral Synthesis? 5
Design Space Exploration 5
ProductivityGains 7
Architecture/ Goal Flexibility 8
Limitations of Behavioral Synthesis 8
Behavioral Design vs. System Design 9
2.2 The RTLDesign Process 10
Developingthe Algorithm 10
ExploringAlternateArchitectures 11
2.3 The Behavioral Design Process 12
ASimpleAlgorithm 14
DataDependencies 14
RTLSynthesis Implementation 15
vi UnderstandingBehavioral Synthesis
Resource Allocation 16
Scheduling 17
Control Logic/ StateMachine 18
Memory 18
DataPath Elements 19
GanttCharts 21
ChainedOperations 22
Multi-cycleOperations 22
2.4 Summary 23
3. The Behavioral Synthesis Process
Chapter3discussesthe steps performed during behavioral synthesis. While
this chapterdiscusses some topics thatare not essential to using behavioral
synthesis tools, a good understanding of these steps will provide insight into
the results produced bybehavioralsynthesis.
3.1 The BehavioralSynthesisProcess 25
3.2 Internal Representations 26
3.3 Resource Allocation 27
3.4 Scheduling 30
Scheduling Concepts 30
ASAP/ALAP Scheduling 30
OtherScheduling Methods 31
3.5 Register Allocation 35
Lifetime Analysis 35
RegisterSharing 36
3.6 Binding 37
3.7 DataPath and StateMachineExtraction 39
3.8 Netlisting 39
ScheduledDesign 39
Final Design 40
3.9 Summary 40
4. Data Types
Chapter 4 discusses the data types that are supported by behavioral
synthesis and how those data types are translated into a gate-level netlist.
The job of any synthesis tool is to ultimately translate all data types to those
datatypes thatcan represent wires.
TableofContents vII
4.1 SynthesisConsiderations 41
4.2 bitI biCvectorTypes 42
4.3 booleanType 43
4.4 std_loglcI std_loglc_vectorI signedI unsignedTypes 43
4.5 IntegerType 47
4.6 EnumeratedType 48
4.7 RecordType 49
4.8 ArrayType 50
4.9 Types NotSupportedforSynthesis 54
4.10 Summary 55
5. Entities, Architectures, and Processes
Chapter 5discusses the fundamental building blocks of a VHDL description.
Designers writing RTL code utilize these building blocks differently than
designerswriting behavioralcode.
5.1 The EntityDeclaration 57
PortsWith AbstractTypes 58
Wrapper Models 60
5.2 The ArchitectureSpecification 64
5.3 Processes 65
Specifying Clock Edges 69
Timing Diagrams 70
Scheduling Assumptions 73
5.4 Summary 76
6. Loops
Chapter6 discusses the role of loops in behavioral descriptions. Unlike RTL
synthesis tools, behavioral synthesis tools support FOR loops with both
constant and non-constant bounds, WHILE,- loops, and infinite loops.
Behavioral synthesis methodologies encourage the use of loops to allow
designersto describe algorithmsatahigherlevel ofabstraction.
n
6.1 LoopsIn RTL Design
6.2 LoopConstructsand StateMachines 79
6.3 The EXITStatement 81
Specifying aSynchronousReset 82
vIII Understanding Behavioral Synthesis
Simulatingthe ResetCondition 83
Complex ResetSequences 85
Using an Attributeto SpecifyaResetSignal 86
Specifyingan Asynchronous Reset 87
6.4 TypesofLoops 88
InfiniteLoops 88
WHILE Loops 89
FOR Loops 91
6.5 TheNEXTStatement 92
6.6 Scheduling Loops 94
ClockCyclesandControl Steps 95
Minimum ExecutionTime 96
6.7 Loop Unrolling 98
CompleteUnrolling 98
Partial Unrolling 100
When to Unroll 101
6.8 Summary 103
7.1/0 Scheduling Modes
Chapter 7 explains I/O scheduling mode terminology, as defined for
behavioral synthesis. I/O modes allowthe userto determinethe relationship
betweenthetiming ofthebehavioral description andthesynthesizeddesign.
7.1 OverviewofScheduling Modes 105
7.2 Cycle-Fixed SchedUling Mode 106
Scheduling aSimple Design 106
Testing Designs Scheduled in Fixed I/O Mode 109
Scheduling Conditional Branches in Fixed I/OMode 109
SchedulingLoops in Fixed I/OMode 114
Advantages and Disadvantagesof Fixed I/OMode 117
7.3 Superstate-Fixed SchedUling Mode 118
Scheduling aSimpleDesign 120
Testing Designs Scheduled in SuperstateI/O Mode 121
Scheduling Conditional Branches in SuperstateI/OMode 124
Scheduling Loops in Superstate I/O Mode 127
Advantages and DisadvantagesofSuperstate I/O Mode 128
7.4 Free-Floating SchedulingMode 130
Scheduling aSimple Design 130
TableofContents ix
Testing Designs Scheduled in Free 1/0Mode 132
Advantages and Disadvantagesof Free1/0 Mode 133
7.5 Summary 134
8. Pipelining
Chapter8explains howpipelining can be used to increase the throughput of
adesign. Pipelining increasesthe throughput of adesign usuallyatthe cost
of area, butthis is notalways necessaryifthedesign is thoroughlyanalyzed.
The useof pipelined components andthepipelining of loops areconsidered.
8.1 Typesof Pipelining 135
8.2 Pipelined Components 135
Design Benefits 137
Design Flow Benefits 140
8.3 Loop Pipelining 142
Scheduling a Pipelined Loop 143
Latencyand Initialization Interval 146
NEXTand EXITStatements ina Pipelined Loop 149
Dependencies in a Pipelined Loop 151
Simulating a Pipelined Loop 152
Restrictionson Pipelined Loops 154
8.4 Summary 154
9. Memories
Chapter 9 discusses how arrays can be mapped to memory. Multi
dimensional arrays can be used in behavioral descriptions to manipulate
groups of data in a direct, easy-to-understand manner. Arrays can be
mapped to avarietyoftypes of memories. This allows the designerto make
intelligentdecisionsaboutan appropriate memoryto include in adesign.
9.1 Memories in RTL Design 155
9.2 Mapping Arraysto Memory 155
Mapping IndicestoAddresses 156
Synchronous Memory 160
Asynchronous Memory 163
MemoryPorts 166
Data Dependencies 167
9.3 Summary 172
x UnderstandingBehavioralSynthesis
10. Functions, Procedures, and Packages
Chapter 10 discusses the role of functions, procedures, and packages in
behavioral design. When placed in a package, functions and procedures
promote reuse, as subprograms in packages can be used in multiple
designs. Functions can also be used to simulate the behavior of complex
blocksthatwill bemappedto pre-constructedcomponentsduring synthesis.
10.1 Subprograms 173
10.2 Functions 174
Mappingtoan Operator 174
Preserving aFunction 176
10.3 Procedures In
10.4 Packages 178
10.5 Summary 180
11. Handshaking
Chapter 11 discusses pre- and post-scheduling simulation issues. A design
that has been validated at the behavioral level must also be validated after
scheduling. The correlation between I/O read and write operations in
behavioral designs and scheduled designs is discussed. A simple
handshaking protocol isintroduced.
11.1 Communication With External Models 181
Scheduling Assumptions 181
Synchronizing CommunicationWith Fixed I/O 182
11.2 Handshaking 184
Full vs. Partial Handshaking 184
InputHandshaking 186
OutputHandshaking 190
Scheduling Issues 191
11.3 InterprocessCommunication 195
11.4 Summary 196
12. ReusableTest Benches
Chapter 12 discusses how to design a test bench that can be used with a
behavioral design, a scheduled RTL design, as well as the resulting
optimizedgate-level design. Thetestbench usesthe handshaking principals
introduced in Chapter11.
