Unconventional electronics design through arti cial evolution

26 Pages·1999·0.57 MB·English

Explorations in Design Space: Unconventional
electronics design through arti(cid:12)cial evolution
Adrian Thompson, Paul Layzell, Ricardo Salem Zebulum
Abstract|Three hypotheses are formulated. First, in the H3 Evolutionary algorithms in practice can produce de-
‘design space’ of possible electronic circuits, conventional
signs that are beyond the scope of conventional methods
designmethodsworkwithinconstrainedregions, nevercon-
sideringmostofthewhole. Second,evolutionaryalgorithms and are, in some sense, better.
can explore some of the regions beyond the scope of con- Note that the truth of each hypothesis relies in part on
ventionalmethods,raisingthepossibility thatbetter designs the truth of the preceding ones. In Section II we attempt
can befound. Third, evolutionary algorithmscan inpractice
to verify the (cid:12)rst hypothesis by characterising what elec-
produce designs that are beyond the scope of conventional
methods,and thatare in some sensebetter. tronics designers normallydo. Being essentially a work of
A recon(cid:12)gurable hardware controller for a robot is anthropology,this isinevitablysubjective andopen todis-
evolved, using a conventional architecture with and with-
pute. We judge that the basic conclusions are robust to
outorthodox designconstraints. Intheunconstrainedcase,
variationsin the exact details of how the designer’s activi-
evolution exploited the enhanced capabilities of the hard-
ware. A tone discriminator circuit is evolved on an FPGA ties are conceptualised.
without constraints, resulting in a structure and dynamics In the case studies of Sections III and IV, the second
that are foreign to conventional design and analysis. The
hypothesis is veri(cid:12)ed empirically,to a high degree of con-
(cid:12)rst two hypothesesare true.
Evolution can explore the forms and processes that are (cid:12)dence. The hierarchical dependency of the hypotheses
natural to the electronic medium, and nonbehavioural re- means that H1 is also strengthened.
quirementscan be integratedinto this design process, such
In the (cid:12)nal section, tools are presented for ongoing re-
as fault tolerance. A strategy to evolve circuit robust-
search to produce circuits through arti(cid:12)cial evolutionthat
ness tailored to the task, the circuit, and the medium, is
presented. Hardware and software tools enabling research are beyond the scope of conventional design, are in some
progress are discussed. The third hypothesis is a good sense better, and that are practically useful. This is the
workingone: practicallyusefulbutradicallyunconventional
third hypothesis. Fromthe experimentalresults, it isclear
evolved circuits are in sight.
that there can be some special ‘niches’ [1] for unusual cir-
Keywords| Evolutionary algorithms, Electronics design,
Design automation,Faulttolerance, Evolutionary theory. cuits, but it remains to be seen how broadly they can be
applied. We interpret our results as encouraging.
I. Introduction
A. Algorithms
MAGINE a design space [1] where each point in that Most of the discussion applies equally to any evolution-
Ispace represents the design of an electronic circuit. All ary algorithm(EA), in fact to any search algorithmbased
possible electronic circuits are there, given the component on a process of ‘generate-and-test’. Since our aim is to
types available to an electronics engineer, and the techno- explore design-space as freely as possible, we avoid incor-
logicalrestrictions on how manycomponents there can be porating heuristics into the search that makesweeping as-
and how they can interact. In this metaphor, we loosely sumptions about the characteristics of desirable circuits.
visualise the circuits to be arranged in the design space so Forperformancesuperiortorandomsearch, however,some
that ‘similar’circuits are close to each-other. domain-speci(cid:12)csearch biases are necessary [2]. Hence evo-
The design space is vast. There are oscillators and (cid:12)l- lutionary searchisused,thebiasofwhich(thatfuturecan-
ters, (cid:12)nite-state machines, analogue computers, parallel didate circuits should be based on variations of the more
distributed systems, von Neumann computers, and so on. successfulearlierones)makesminimal|butnotnegligible
These nestle amongst the majority of circuits for which a | assumptions as to the nature of the circuit itself.
use will never be found. In this paper, we investigate the Biases also arise, often unintentionally, from the circuit
followinghypotheses: representationtowhichtheoperatorsareapplied. Skewsin
H1 Conventional design methods can only work within the number of points representing each circuit (or type of
constrained regions of design space. Most of the whole circuit),andclusteringofcircuittypesintherepresentation
design space is never considered. with respect to the operators, can both bias the searching
H2 Evolutionary algorithms can explore some of the re- of even a simple (1+1) evolution strategy [3]. For many
gions indesign space that are beyond the scope ofconven- EAs, the local gradient of (cid:12)tness with respect to the oper-
tionalmethods. Inprinciple,thisraisesthepossibilitythat ators can bias the direction of search, for exampletowards
designs can be found that are in some sense better. relatively ‘smooth’ parts of the (cid:12)tness landscape [4], [5].
Whether helpful or adverse for search e(cid:14)cacy, such biases
Centre for Computational Neuroscience and Robotics, and Cen- arenoteasilyavoided,butcansometimesbeturnedtospe-
tre for The Study of Evolution, School of Cognitive & Computing
Sciences,UniversityofSussex,BrightonBN19QH,UK.(email: adri- ci(cid:12)c uses such as giving graceful degradation properties to
anth,paulla,[email protected]) evolved circuits [6].
Later, when more of the uncharted territory of design- temperature
space has been investigated, the performance of the EA
EMI
might be improved by incorporating this heuristic knowl-
edge into the circuit representation, or the variation and
selection operators. In this paper we use basic genetic al-
gorithms(GAs),oftenwithverydirect ‘genetic’encodings. fabrication
This is to aid clarity in describing the experiments, and variations
does not imply that these GAs are particularly e(cid:11)ective
EAs forthese tasks. Note thatatanygiventime,anEA is
searching over accessible variations rather than the entire supply
etc
design-space [7]; no attempt is made at global search, but voltage
instead at the exploration of new regions.
Fig.1. Visualisinganoperationalenvelope.
B. The Objectives of Circuit Design
The objectives of circuit design can be divided into be-
is designed so as to be rapidly and rigourously testable,
haviouraland nonbehavioural requirements:
and able to be easily modi(cid:12)ed to (cid:12)x design or speci(cid:12)ca-
Behavioural requirements de(cid:12)ne the desired interaction
tion errors, then time to market is reduced. Additionally,
betweenthecircuitanditsexternalenvironment. Onepos-
aproduct lifecycleoften includesthe release ofupdates, or
sibilityistodescribe therequired behaviourdirectlyatthe
speciallycustomisedversions oftheoriginaldesign,requir-
interface between the circuit and environment in the form
ingareadilymodi(cid:12)abledesign. Finally,engineeringdesign
of a relationship between inputs and outputs over time:
isoftenaprocess of‘designexploration’[9]inwhichpartial
‘Direct behavioural requirements’. Another is to de(cid:12)ne the
attemptstosolvetheproblemare used iterativelytore(cid:12)ne
desired behaviour ofalarger system inwhich the circuit is
the requirements speci(cid:12)cation into a useful form.
embedded: ‘Embedded behavioural requirements’. An ex-
Hence a circuit must be evaluated according to many
ample of the latter would be to de(cid:12)ne the required be-
di(cid:11)erent criteria. Forexample,there can be asmanyas 20
haviour of a robot that the circuit controls, rather than
di(cid:11)erentcriteriacomposingtherequirementsforacommer-
de(cid:12)ning the input/output relationship of the controller it-
cialoperationalampli(cid:12)er,[10],[11]. Typically,someofthe
self. The need to keep electromagnetic emissions within
criteria should be maximised or minimised, while others
acceptable limits is often thought of at both direct and
provide hard constraints. EA methods for multi-criteria
embedded levels: guidelines for the emissions of subsys-
[12] and constrained optimisation [13] are well developed
tems, combined with principles for systems-level design to
andthere ispotentialforthemtobeadaptedandextended
guarantee overall performance [8].
for electronics design [14],[15],[16],[17],[18],[19],[20].
Nonbehavioural requirements de(cid:12)ne the resources that
are available to the circuit, and the environmental condi-
C. Unconstrained Evolutionary Electronics
tions under which it must continue to operate for some
minimum lifetime at a given maximum failure rate. Ex- Inthispaper,the‘unconstrained’approachtoevolution-
amplesof resources are size (silicon or circuit-board area), ary electronics is developed. We deliberately seek to ex-
weight,power consumption,and construction cost. Exam- plore beyond the scope of conventional design in the hope
ples ofpossiblyrelevantenvironmentalconditionsare tem- of (cid:12)ndingcircuits that are in some waysuperior in a prac-
perature, output load, power-supply voltage, fabrication tical setting, according to some combination of the many
variations, defects (needing fault tolerance), electromag- criteria above. Thiswas stated as hypotheses H1{3,where
netic interference (EMI), humidity,and mechanical vibra- whatismeantby ‘insomesense better’ hasnowbeen clar-
tion. The combinationsand ranges of such environmental i(cid:12)ed.
variablesunderwhichthecircuitmustmeetitsbehavioural Theneedtoreducedesigntimeandcostmeansthatelec-
requirements can be thought of as de(cid:12)ning its operational tronicsdesignautomationthroughEAs couldbepro(cid:12)table
envelope: a set of points in a space spanned by the envi- even ifconstrained to workwithinthe samesphere ascon-
ronmental variables. As an operational envelope consists ventional design. By concentrating on the unconstrained
partly of ranges of environmental variables, it can be vi- case, however, weaimtomapoutthe boundaries andben-
sualised usefully in terms of regions for correct operation e(cid:12)ts of the evolutionaryapproach, without blindlyaccept-
(Fig.1). In general, an operationalenvelope maybe of ar- ing the constraints inherited from conventional design. It
bitrary structure, so this visual metaphor should be used is not claimedthat all unconventionalevolved circuits will
with care. be practically useful;it is claimedthat toreject alluncon-
Wedescribe acircuitthat performsadequately through- ventional circuits solely because they cannot be arrived at
out the operational envelope de(cid:12)ned for its task as being through conventional design methods is premature.
robust. Theargumentthatconventionaldesignis constrained in
Notincluded aboveistheneed tominimisethetimeand a way that evolutionary design need not be, in principle,
cost of the design process. At (cid:12)rst sight this is not a re- is given in the next section. This is hypothesis H1. To
quirement on the circuit itself, but in fact if the circuit show that this can allowa practical EA to (cid:12)nd new useful
v +Vdd v
The second is that digitalsystems, especially binary ones,
are extremely tolerant to corruption of the signals. This
is because ofthe signalrestoration to an attractor state at
almostevery opportunity. It is relatively easy to make bi-
nary digitalcircuits with a huge operational envelope. For
t t example, if a signal is corrupted by noise, or an attrac-
tor state of an element’s output drifts with temperature,
there are large margins for error, as seen in Fig. 2. In
Fig. 2. Voltage/time waveforms exemplifying the operation of a synchronous circuits, there also needs to be a margin for
CMOSNOTgate(centre). Shownattheleftistheinput,andat
error included in the clock period: the time for an output
therightisthecorrespondingoutput.Thegrayregionsrepresent
thebasinsofattractionofthetwoattractorstates. to be computed, stabilise, and be transferred to the next
subcircuit mayvary within the operational envelope.
These advantages come at a cost. The basic elements
circuits is an empirical matter (H2). Hence a pair of case
must all have the signal-restoring property. The system
studies is presented. Finally, research tools are described must be broken down into subcircuits that are simple
that are being used to illuminate whether unconventional
enoughforinternaltransientsnottobeaproblem. Usually
evolved circuits really can be of engineering bene(cid:12)t, when
this means that the subcircuits are basically feedforward
judgedbythemanycriteriaofapracticalapplication(H3).
or ‘combinatorial’ (having no feedback or recurrent loops
within them). The communications between the subcir-
II. Characterising Conventional Design
cuits mustbe carefully regulated, usuallyby meansofreg-
First, we consider separately the two electronics isters that only load in new values when communications
paradigms: digital and analogue. Then the process of de- are to be permitted (subcircuits have stabilised). Digital
sign within those paradigmsis discussed. design,byusingthe componentsonlyasswitchingdevices,
mustimposethese design constraintstosuppress the other
A. Digital Design aspects of the analogue, continuous-timereality.1
Inadigitaldesign,whenever asignalisused oroperated
B. Analogue Design
upon,itisrounded o(cid:11)tothe closest oneofa(cid:12)nitenumber
of attractor states. Usually,there are two attractor states, Analoguedesign(cid:12)ndsanalogiesbetweenthephysicalbe-
situated atthe upper andlowerextremes ofpossible signal haviour ofgroups of electronic components and the opera-
levels: binarylogic. Wheneveranewormanipulatedsignal tionsneeded toconstruct the desiredsystem. Toallowthis
isgenerated,itisatoneoftheattractorstates. Fig.2shows exploitation of the natural behaviours of groups of com-
the operation of a binary NOT gate made from CMOS ponents, internal signals are mostly of continuous-value,
transistors. in contrast to digital design. Although not unprincipled,
It takes a nonzero time for an input to change fromone analoguedesignisoftenthoughtofasmoreofan‘art’com-
state to another. During this time,and brie(cid:13)y afterwards, pared to digital design. Even many predominantly digital
the fundamentally analogue nature of the transistors im- systems require some analogue circuitry at least to deal
plementinga logicelementis revealed at its output, which with the interface to the world.
is to be seen brie(cid:13)y at levels between attractor states, pos- Analoguedesigncanextract morefunctionalityfromthe
sibly even making multiple transitions before quickly set- components than can digital, because more of the compo-
tling into the appropriate attractor state (‘switching tran- nents’ behaviour is put to use. Especially potent is the
sients’). use of real time, rather than representing time as a com-
In a digitalcircuit, madeas a network oflogicelements, putational variable like any other, as in digital systems
precautions must be taken to ensure that switching tran- [24], [25]. For some tasks (where ‘task’ includes nonbe-
sients do not a(cid:11)ect the overall behaviour of the system. haviouralrequirements)analoguedesignisclearlysuperior.
This is done by some method of phase control between In other cases, the choice of analogue or digital design is
parts of the system, so that a subcircuit is not allowed to also strongly in(cid:13)uenced by the ease of the design process
use the output of another until it has settled at the cor- itself, which often favours digital.
rect attractor state. In asynchronous logic design, local The disadvantages of analogue design are the obverse
handshaking signals are used between subcircuits [21]. In of the advantages of digital design identi(cid:12)ed above. Al-
synchronous logic, one or more regular ‘clock’ signals is thoughsystem-leveldesigncanbeatanabstractlevel,ana-
used to control when subcircuits can communicate. The loguecircuit design mustnecessarily consider properties of
frequency of a clock is chosen such that the slowest sub- the physical components,and their interactions, ingreater
circuit it controls has time for its output to settle at the 1
Although charge is quantised, and these charges often move
correct state between ‘ticks’.
throughperiodicatomiclatticeshavingdiscreteenergylevels,atthe
There are two main advantages to digital design. The scaleaddressedbycontemporarycircuitdesignwemayconsidercur-
(cid:12)rst, to be elaborated in xII-C, is that most of the design rentsandvoltagesascontinuous[22]. Thiscouldchangeinthefuture
if meso/nano-scale electronics becomes practical; it might then be
can be considered at the level of logical algebra, without possibletoexploitphysicalquantisationtoimplementdigitalcompu-
having to think about the physics of electronic devices. tations[23].
B.B. B.B. B.B.
serves solelytocompensateforthethermalvariationofthe
base-emitter voltage of Q1. Under certain well-analysed
B.B.
conditions, this building block can be used to serve the
function ofacurrent-sink over a range oftemperatures, ir-
respective of what the rest of the system is doing. If all of
+Vcc
the other buildingblocks are similarlyendowed with ther-
load mal stability of function, and are composed so as not to
violate their constraints of operation, then the whole cir-
Q2 cuit can be given thermal stability. Although there are
stillpitfalls,the designofcomplexrobust analoguecircuits
Q1
would be practically infeasible without this approach.
C. The Design Activity
Wehaveseenthatbothdigitalandanaloguedesignstyles
are, in practice, restricted as to what kinds of circuits can
be produced. Digital designs must be made of signal-
Fig.3. Exampleofthe‘BuildingBlock’(B.B.)approachinanalogue
design. restoring elements regimented into subcircuits of simple
dynamics, with constrained moments of communication.
Analogue designs are made mostly of standard building
depth than for digital design. The second disadvantage is blocks, with the rare creation of a completelynovel design
that stabilityand large noise marginsare more di(cid:14)cult to usually being restricted by design-di(cid:14)culty to the level of
guarantee. these smallsubcircuits.
Sarpeshkar [26]shows that as the complexityof an ana- Furtherpracticaldesignconstraintsarisefromthechoice
logue system increases, it becomes essential for signal val- of design (cid:13)ow. A design (cid:13)ow starts with high-level design
ues to be restored to attractor states occasionally, oth- decisions about the gross structuring of the system, and
erwise all of the signal would eventually be swamped by ends with exact details of how it should be implemented.
unavoidable noise. This signal restoration does not hap- In-betweenarestagesofproblemdecomposition,andapro-
pen at every circuit element, as it does in digital systems, gression fromconsidering the problemata highlyabstract
and the representation of the analogue signal may be dis- level,through to reifyingthe design to the concrete details
tributed across more than one physical voltage, current, of implementation. The particulars of a design (cid:13)ow are
or charge. There is (cid:13)exibility in the choice of restoration strongly in(cid:13)uenced by the computer-aided design (CAD)
schemes,notlimitedtotwoattractorstates,andnotneces- tools available for each step, and the ease with which dif-
sarilyuniformthroughoutthesystem. Sarpeshkarprovides ferent tools can be integrated.
a costs/bene(cid:12)ts analysis for some restoration schemes un- Design-automationtoolsare highlydeveloped fordigital
der variousresource constraintsandoperationalenvelopes, systems, and far less so for analogue. Rutenbar [28] sees
with reference to neural systems; it appears that there is the impedimentto analogue design automationas the dif-
greatuntappedpotentialinanalogue(or‘hybrid’)electron- (cid:12)culty of providing a library of ‘standard cells’ adequate
ics, if new design styles could be developed. to implement an arbitrary user design fully. A standard
In practice, analogue design is currently based around cell isan implementation buildingblock,completelyspeci-
the use of ‘building block’ subcircuits. These have been fyingcomponentdetails,placement,androutingtoachieve
carefullydesignedandanalysedinthepasttoperformgen- a precise function: this is di(cid:11)erent from the more generic
erallyusefulfunctions,andforma‘cookbook’withwhicha architectural design building blocks mentioned above. We
largerdesigncanbeconstructed. Adesignertakesbuilding have already indicated that it is inherent in an analogue
blocks from textbooks, and from looking at other circuits design process that it is moredi(cid:14)cult to abstract function
designedforsimilarproblems. Examplesofbuildingblocks fromimplementation,than for digital systems.
areampli(cid:12)ers,(cid:12)lters,oscillators,voltageorcurrentsources, Evolutionary algorithms have been applied as design-
and many others. The original design of a building block automation tools at various levels of abstraction: Table I
canbeverychallenging,oftenbeyondthecapabilitiesofde- gives some examples for a digital design (cid:13)ow. Top-down
signers who later use them. Without building blocks, the design of this sort is ubiquitous, and almostindispensable
design of complexanaloguesystems wouldbe too di(cid:14)cult. for large systems, but does impose constraints of its own
The use of building blocks is not only to avoid ‘re- on what circuits can be produced. ‘Abstraction’ implies
inventing the wheel’ for each design. By compartmental- the suppression of somedetails;design at anabstract level
ising the circuit into functional packages with well-de(cid:12)ned thereforerequiresconstraintofthoseneglecteddetailsupon
interfaces, it becomes easier to make the whole circuit ro- progression towards the concrete implementation.
bust across an operational envelope. Taking thermal sta- For the current enterprise, we seek to explore design-
bility as an example, Fig. 3 shows a hypothetical system space as freely as possible, even if in doing so we can only
composed of building blocks. The enlarged subcircuit is work with relatively small circuits in practice. Once the
a standard current-sink building block [27]. Transistor Q2 potential of new territories in design space is ascertained,
TABLE I
are closelycoupled bothwithgeneraldesign decisions, and
Some stepsin a digital designflow towhich EAshave been
with details of the implementation. In a top-down design
applied.
(cid:13)ow, implementation details are not fully contemplated
Design activity EA Level during the early | more abstract | stages, making de-
example sign for nonbehavioural requirements problematic. An ex-
ampleof integratingafault-tolerance (nonbehavioural)re-
quirementwithembeddedbehaviouralrequirementswillbe
Partitioning into [29] Abstract
given in xIII-C. It is partly the ability to embrace nonbe-
hardware and
haviouralrequirementsduringall stagesofanevolutionary
software modules
design process, in combinationwith an exploration of new
circuit structures and dynamics, that provides the oppor-
2
tunity for better circuits to arise through evolution (H3).
Design of a [30]
By diagnosing the constraints of conventional design |
network of
w fromthe analogue and digitaldesign paradigms,and from
high-level functions (cid:127)
top-downdesign(cid:13)ows|hypothesisH1isshown. Itisalso
deduced that an evolutionary approach, in principle, can
explore some regions in design space that are beyond the
Function behaviour [31]
scope of conventional methods. This is not su(cid:14)cient for
7(cid:0)! Net of logic
hypothesis H2: we need to go on to demonstrate an evo-
w
gates (cid:127) lutionary algorithm exploring new regions. That is done
through a pair of case studies carefully formulated for the
purpose, presented in the next two sections. During these
Net of logic gates [19] case studies, the need to deal with a realistic set of re-
7(cid:0)! Choice froma
quirements is temporarily neglected. In the (cid:12)nal section,
w
library of physical (cid:127) ongoingwork to address this is described, movingtowards
components
hypothesis H3: thepracticalevolutionofrobustunconven-
tional electronics.
Net of physical [32] Concrete III. Case Study 1: Removing dynamical
components 7(cid:0)! [33] (implementation) constraints from a standard architecture
Placed and routed
Inthis(cid:12)rstcasestudy,astandardelectronicarchitecture
VLSI layout
istaken, andthe temporalconstraints associated withdig-
italdesign are relaxed,andplaced under evolutionarycon-
trol. Thisallowsadirectcomparisonofthebehaviouralca-
pabilitiesofthesamehardwarewhensubjected to,orfreed
this knowledge can be fed back into the domain of top- from, design constraints. Integration of a nonbehavioural
down design, perhaps as additions to the designer’s ‘cook- requirement for fault tolerance with the behavioural re-
book’ of subcircuit ideas. The variation operators, or the quirements is then discussed. The behavioural require-
representation of the circuit on which they operate, may ments are an example of the embedded type, where it is
be designed to encourage modularity and repeated struc- the performance of an electromechanical system in which
tures, aiding the evolutionaryprocess in the production of the circuit is embedded that is evaluated.
large systems [34], [35]. For the present, we apply evolu-
A. The Experiment
tionary algorithmsin a bottom-up fashion, with the EA’s
variationoperatorsmanipulatingthestructureatthe(cid:12)nest The circuit to be evolved was the onboard con-
level of implementationdetail available. Constraints asso- troller for the robot shown in Fig. 4 [37]. This two-
ciated withtheconventionaldigitaloranalogueparadigms wheeled autonomousmobilerobot hasadiameterof46cm,
are resisted as being prejudicial for evolution. In general, a height of 63cm, and was required to display sim-
the circuits are continuous-time, continuous-value dynam- ple wall-avoiding/room-centering behaviour in an empty
ical systems; digital, analogue, and hybrid circuits are all 2.9m(cid:2)4.2m rectangular arena. For this scenario, the dc
includedinthisrepertoireofpossibilities. Noclaimismade motors were not allowed to run in reverse and the robot’s
thatmore ofdesignspacecanpracticallybesurveyed(that only sensors were a pair of time-of-(cid:13)ight sonars rigidly
mayor maynot be the case), but rather new regions. mountedontherobot,onepointingleftandtheotherright.
Here, there is no distinction between design and imple- The sonars (cid:12)re simultaneously(cid:12)ve timesa second; when a
mentation: the process of evolutionary design happens at sonar (cid:12)res, its output changes from logic 0 to logic 1, re-
the implementation level. As well as avoiding abstrac-
2
tion constraints, this facilitates the integration of non- It is not essentialto adopt such a radicalunconventionalstance
to begin to tackle this issue. For instance, Miller & Thomson [36]
behavioural and behavioural requirements. Many nonbe- incorporategeometriclayoutconsiderationsintoevolutionarydesign
haviouralrequirements,suchassizeorpower-consumption, ofdigitallogic.
Sonars Evolved RAM Contents
Virtual
World
Simulator
1k by 8 bits RAM
10 Address inputs 8 Data outputs
1 1 10 6 1 1
O.L.
Sonar
Emulator
Reconfigurable
DSM circuit
O.L.
Sonars Evolved M M
Clock
(left & right) Motors
Wheels
Fig. 5. The hardwareimplementationof the evolvableDSM robot
(left & right) controller. ‘Optionallatches’(O.L.)controlwhethereachsignal
ispassedstraightthroughasynchronouslyasananaloguevoltage,
orwhetheritsdigitalvalueislatchedaccordingtotheglobalclock
ofevolvedfrequency.Eachoptionallatchwasimplementedusing
an analogueswitch chip able to bypass a clockedlatch. A full
Rotation
circuitdiagramisgivenin[39].
Sensors
Fig.4. Therobotknownas‘MrChips.’ sult(Fig.5),isamachineofadi(cid:11)erent nature. Notonlyis
the global clock frequency placed under evolutionary con-
trol, but the choice of whether each signal is synchronised
turningto0when the(cid:12)rst echoissensed atitstransducer. (latched) by the clock or whether it is asynchronous (di-
Conventional electronic design would tackle the control rectly passed through as an analogue voltage) is also de-
problem along the following lines: for each sonar, a timer termined by evolution. These relaxations oftemporalcon-
would measure the length of its output pulses | and thus straints | constraints necessary for a designer’s abstrac-
thetimeof(cid:13)ightofthesound|givinganindicationofthe tion but not for unconstrained evolution | o(cid:11)er a rich
rangetothenearestobjectonthatsideoftherobot. These range of potential dynamical behaviour to the system, to
timers would provide binary-coded representations of the the extent that the sonar echo pulses can be fed directly
twotimesof(cid:13)ightto acentral controller. The central con- in, and the motors driven directly by the outputs, with-
trollerwouldbeahardwareimplementationofa(cid:12)nite-state out any pre- or post-processing: no timers or pulse-width
machine (FSM), with the next-state and output functions modulators. (The sonar (cid:12)ring cycle is asynchronous to the
designedsothatitcomputesabinaryrepresentation ofthe evolved clock.)
appropriate motorspeed foreach wheel. Foreach wheel, a Letthisnewarchitecture becalledaDynamic State Ma-
pulse-width modulator would take the binary representa- chine (DSM).Itisnot a(cid:12)nite-state machinebecause ade-
tionofmotorspeedfromthecentralcontrollerandvarythe scriptionofitsstatemustincludethetemporalrelationship
mark:space ratio of pulses sent to the motor accordingly. between the asynchronous signals, which is a real-valued
ItwouldbepossibletoevolvethecentralcontrollerFSM analogue quantity. In the conventionally designed control
by implementing the next-state and output functions as system there was a clear sensory/control/motor decom-
look-uptables heldinano(cid:11)-the-shelf randomaccess mem- position(timers/controller/pulse-width-modulators),com-
ory (RAM) chip; this is the well-known ‘Direct Addressed municatingin atemporal binary representations which hid
ROM’ implementation of an FSM [38]. The FSM would the real-time dynamics of the sensorimotor systems, and
then bespeci(cid:12)ed bythebitsheldintheRAM,whichcould the environment linkingthem, fromthe central controller.
berecon(cid:12)guredunderthecontrolofeachindividual’sgeno- Now, the evolving DSM is intimately coupled to the real-
type in turn. Such evolution would still be subject to the time dynamics of its sensorimotor environment, so that
constraints ofdigitaldesign: allof the signals are synchro- real-valued time can play an important role throughout
nised to a global clock to give clean, deterministic state- thesystem. TheevolvingDSMcanexplorespecial-purpose
transitionbehaviouraspredictedbyanabstractedBoolean tight sensorimotor couplings because the temporal signals
model. can quickly (cid:13)ow through the system being in(cid:13)uenced by,
Whatifthe constraint ofsynchronisationofallsignalsis and in turn perturbing, the DSM on their way.
relaxed and placed under evolutionary control? Although For the simplewall-avoidancebehaviour, only the outer
super(cid:12)cially similar to the FSM implementation, the re- two of the eight feedback paths seen in Fig. 5 were en-
LEFT RIGHT If the distance of the robot fromthe centre of the arena
MOTORS M M inthexandy directionsattimetwascx(t)andcy(t),then
after an evaluationfor T seconds, the robot’s (cid:12)tness was a
discrete approximationto the integral:
T 2 2
1 (cid:0)kxcx(t) (cid:0)kycy(t)
(cid:12)tness = e +e (cid:0)s(t) dt (1)
T 0
Z (cid:16) (cid:17)
FULNOCGTIICON FULNOCGTIICON kx and ky were chosen such that their respective Gaus-
sian terms fell from their maximum values of 1.0 (when
the robot was at the centre ofthe arena) to a minimumof
0.1 when the robot was touching a wall in their respective
directions. The function s(t) encourages continual move-
ment, having the value 0 when the robot is moving,but 1
otherwise. Each individualwas evaluated for four trials of
30 seconds each, starting with di(cid:11)erent positions and ori-
entations. The worst of the four scores was taken as the
(cid:12)tness [44]. For the (cid:12)nal few generations, the evaluations
were extended to 90 seconds, to (cid:12)nd controllers that were
not onlygood atmovingawayfromwalls,but alsostaying
away fromthem.
LEFT RIGHT
For convenience, evolution took place with the robot in
SONARS
a kind of ‘virtual reality.’ The real recon(cid:12)gurable DSM
circuit controlledthe realmotors,but the wheels were just
Fig.6. AnalternativerepresentationoftheevolvableDynamicState spinning in the air. The photograph of Fig. 4 was taken
Machine,as usedin theexperiment. Each is an‘optional duringanactualevolutionaryrunofthiskind. Thewheels’
latch’(seeprevious(cid:12)gure).
angular velocities were measured, and used by a real-time
simulation of the motor characteristics to calculate how
the robot would move if on the ground. The sonar echo
abled, feeding the RAM chip’s two least-signi(cid:12)cant data signals were then arti(cid:12)cially synthesised and supplied in
bits back to its two least-signi(cid:12)cant address inputs. The real time to the hardware DSM. Realistic levels of noise
resulting DSM can be viewed as the fully connected, re- were included in the sensor and motor models, both of
current, mixed synchronous/asynchronous logic network which were constructed by (cid:12)tting curves to experimental
shown in Fig. 6, where the bits stored in the RAM give measurements, including a stochastic model for specular
alook-uptableimplementinganypairoflogicfunctions of sonar re(cid:13)ections. Full details are given in [39]. The GA
four inputs. This continuous-timedynamicalsystem could andthe virtualenvironmentsimulationwere performedby
not be simulated in software easily, because the e(cid:11)ects of a laptop PC onboard the robot, and a pair of microcon-
the asynchronous variables and their interaction with the trollers synthesised the sonar and clock waveforms. The
clocked ones depend upon the characteristics of the hard- real DSM hardware connected tothe real motorswas used
ware: metastability[40], [41] and glitches will be rife, and atalltimes. Foroperationintherealworld,therealsonars
the behaviour will depend upon physical (analogue) prop- were simplyconnected in place of the simulatedones, and
erties of the implementation, such as propagation delays, the robot placed on the ground.
metastability constants, and the behaviour of the RAM Fig.7 shows the excellent performance attained after 35
chip when connected in this unusual way. Similarly,a de- generations, withagoodtransfer fromthe virtualenviron-
signer wouldonly be able to work within a smallsubset of ment to the real world. The robot is drawn to scale at its
thepossibleDSMcon(cid:12)gurations|theonesthatareeasier starting position, with its initial heading indicated by the
to analyse. arrow; thereafter only the trajectory of the centre of the
AsimpleGAwasused,withalinearbit-stringgenotype, robot is drawn. The bottom-right picture is a photograph
point-mutations, single-point crossover, linear rank-based of behaviour in the real world, taken by double-exposing
selection, and elitism[42]. The contents ofthe RAM(only (1) a picture of the robot at its starting position, with (2)
32bits required forthe machinewith twofeedback paths), a longexposure ofalight(cid:12)xed on top ofthe robot moving
the period of the clock (16 bits in a Gray code, giving a inthedarkened arena. Ifstarted repeatedly fromthesame
clock frequency from around 2Hz to several kHz) and the positioninthe realworld,the robot followsadi(cid:11)erent tra-
clocked/unclocked condition of each signal (1 bit per sig- jectory each time (occasionally very di(cid:11)erent) because of
nal) were directly represented as contiguous segments of real-world noise. The robot displays the same qualitative
the genotype. The population size was 30, probability of range of behaviours in the virtual world, and the bottom
crossover0.7pero(cid:11)spring,andthebit-wisemutationprob- picturesofFig.7weredeliberatelychosentoillustratethis.
abilitywassetsuchthattheexpected numberofmutations Given that this miniscule electronic circuit receives the
per o(cid:11)spring was one [43]. raw echo signals from the sonars and directly drives the
Left motor ON Left motor ON
Right motor ON Right motor OFF
01 00,10
11 01 01,11
01,11 11
RESET Left motor OFF 00 Left motor OFF
Right motor OFF Right motor ON
00,01
Fig. 8. A representationof one of the wall-avoidingDSMs. Asyn-
chronoustransitionsare shown dotted, and synchronoustransi-
tions solid. The transitionsare labelledwith (left, right) sonar
inputcombinations,andthosecausingnochangeofstatearenot
shown. There is more to the behaviour than is seen immedi-
ately in this state-transitiondiagram,becauseit is not entirely
a discrete-timesystem, andits dynamicsare tightlycoupledto
thoseofthesonarsandtherestoftheenvironment.
Fig.7. Wallavoidanceinvirtualrealityand(bottomright)inthereal
world, after35 generations. The top picturesare of 90 seconds is consistent with the behaviour, but it would have been
ofbehaviour,thebottomonesof60seconds.
very di(cid:14)cult to predict the behaviour from the diagram
because of the rich feedback through the environment and
sensorimotorsystemsonwhichthismachinerelies. Thebe-
motors (one of which happens to be more powerful than
havioureven involvesastochastic component,arisingfrom
the other), the performance is surprisingly good. It is not
the probabilities of certain combinations of the machine’s
possible forthe DSM directly todrive the motorsfromthe
mixed synchronous/asynchronous state, at the arrival of
sonar inputs (in the manner of Braitenberg’s ‘Vehicle 2’
pulses fromthe clock and the asynchronous sonars.
[45]), because the sonar pulses are too short to provide
enough torque. Additionally, such naive strategies would The DSM underlies a non-trivialrobot behaviour, using
failinthe symmetricalsituations seen at the top ofFig.7. minimal resources [46], by means of the circuit’s rich dy-
One of the evolved wall-avoidingDSMs was analysed (be- namics and exploitation of the hardware (an idea dating
low), and found to be going from sonar echo signals to backto 1949[47]). After relaxingthe temporalconstraints
motor pulses using only 32 bits of RAM and 3 (cid:13)ip-(cid:13)ops necessary to support the designers’ digital abstraction, a
(excluding clock generation): highly e(cid:14)cient use of hard- tiny amount of hardware has been able to display rather
wareresources, madepossiblebytheabsenceofdesigncon- surprising abilities. As a control experiment, three GA
straints. runs were performed under identical conditions, but with
alloftheoptionallatchessetto‘clocked’irrespectiveofthe
B. Analysis genotype. Allthree runsfailedcompletely,con(cid:12)rmingthat
new capabilities had been released from the architecture
Fig. 8 attempts to represent one of the wall-avoiders in
when the dynamical constraints were relaxed. In another
state-transition format. This particularindividualused an
setofthree controlruns,alltheoptionallatchesweresetto
evolvedclockfrequencyof9Hz(abouttwicethesonarpulse
‘unclocked.’ These runs succeeded but the behaviour was
repetition rate). Both sonar inputs evolved to be asyn-
not so reliable: from time to time the robot would head
chronous, and both motor outputs clocked, but the inter-
straight for a walland crash into it.
nal state variable that was clocked to become the left mo-
tor output was free-running (asynchronous), whereas that In three repetitions of the main experiment, the clock
which became the right output was clocked. In the dia- allowed the mixed synchronous/asynchronous controllers
gram, the dotted state transitions occur as soon as their to move with a slight ‘waggle’ (just visible in the bottom-
inputcombinationispresent, butthe solidtransitionsonly right picture in Fig. 7), and this prevented them from be-
happen when their input combinations are present at the ing disastrously fooled by specular sonar re(cid:13)ections. The
same time as a rising clock edge. Since both motor out- sonars were e(cid:11)ectively scanning the walls slightly because
puts are synchronous, the state can be thoughtof as being of the waggling movement of the robot body. This sug-
sampled by the clock to become the motoroutputs. gests that while removingan enforced clock can widen the
This state-transition representation is misleadinglysim- repertoire of dynamical behaviours, providing an optional
ple in appearance, because when this DSM is coupled to clock of evolvable frequency, to be used at points in the
the input waveformsfrom the sonars and its environment, circuit determined by evolution,can expand the repertoire
its dynamicsare subtle, and the strategy being used is not of dynamics still further. The clock becomes a resource,
obvious. Itispossibletoconvinceoneselfthatthe diagram not a dynamicalconstraint.
Fitness
C. Integratinga Nonbehavioural Requirement of FaultTol-
1.60
erance
1.40
In Section II-C we described the worth of integrating
nonbehavioural requirements into the objectives during 1.20
evolutionary design. Some nonbehavioural characteristics,
1.00
such as size or power consumption,are usually easilymea-
surabletobecomefactorsintheselectionprocess[14]. Oth-
0.80
ers can be impractical to measure directly, but sometimes
the evaluationprocedure can be contrived so that they ex- 0.60
ert an implicit in(cid:13)uence on (cid:12)tness. As an example, we
0.40
consider introducing a fault tolerance requirement for the
DSM robot controller. Evolutionary techniques for fault- 0.00 100.00 200.00
tolerant electronics are largely unexplored, but the engi- Generations
neering bene(cid:12)ts on o(cid:11)er are signi(cid:12)cant [48],[49],[6].
The requirement is for the controller to be tolerant to
Fig.9. Maximumandmean(cid:12)tnessinthepopulationovertime. The
any adverse single-stuck-at (SSA) fault in the memoryar- (cid:12)rst 85 generationswere in the absenceof faults, thereafterall
ray of the RAM chip, causing a bit to read the opposite (cid:12)tnessevaluationswereinthepresenceofthe‘currentfault’.
of the value written to it. These faultsare easily emulated
by inverting one of the bits speci(cid:12)ed by evolution as it is
bythis consensus sequence wasthen tested inthe presence
written to the chip. Altering the con(cid:12)guration is a gen-
of each of the 32 possible adverse SSA faults in turn. The
erally applicable way to emulate some classes of faults in
fault that caused the consensus individual to behave the
recon(cid:12)gurable hardware; ifthecircuits are beingevaluated
most poorly (lowest (cid:12)tness score) was nominated as the
in software simulationsthere is even more (cid:13)exibility.
‘current fault.’ Another generation of evolution was then
Ideally, for each (cid:12)tness evaluation an individual would
performed,butwiththe current faultbeingpresent during
be given a trial in the presence of every possible fault in
allofthe (cid:12)tness evaluations. After thisgenerationthe new
turn,andtheresulting(cid:12)tnessscorewouldbesomemeasure
consensus individual was constructed, tested, and a possi-
of performance in the face of any fault. However, there
bly new current fault nominated for the next generation.
areusuallymanypossiblefaults,makingexhaustivetesting
Theprocess continuedinthisway,withasinglefaultbeing
prohibitively time consuming (but not always [50]). Even
present throughout all evaluations within a generation |
fortheDSMrobotcontroller,testingeachindividualinthe
thisfaultbeingthe one thatcaused the worst performance
presence ofthe 32emulatedadverse SSA faultswouldtake
in the consensus individualof the previous generation.
too long.
Fig. 9 shows that the maximum and mean (cid:12)tnesses
If the goal is to optimise worst-case performance (i.e.
dropped sharply at generation 85 when faults were (cid:12)rst
minimise the e(cid:11)ects of the most serious fault), there is a
introduced, but over the course of the next 150 genera-
potential shortcut. In this case the (cid:12)tness measure willbe
tionsreturned tohighvalues. Fig.10shows that when the
based on performance in the presence of only the single
faultswere (cid:12)rst appliedthe controller wasalready tolerant
mostserious fault. Ifsomewayofpredicting whichfaultis
tomostSSAfaults,butthatafewwerecritical. Atvarious
the most serious can be found, then only this single fault
stages afterwards, this tolerance to mostSSA faultsis lost
needs to be introduced during the (cid:12)tness evaluation. A
intheGA’sattemptstoimproveperformanceonthesingle
similar situation arises if only a relatively small subset of
most serious current fault. Some serious faults are seen to
the possible faultsseriously degrades the system: onlythis
persist over long periods. Eventually, consensus individu-
subset need be considered.
als arose that give satisfactory performance when any of
However,which faultsarethe mostserious mightbe dif-
3
the SSA faults is present. Fig. 11 compares the fault tol-
ferent for each individual in the population. If the only
erance of the conventionally-evolved consensus individual
way to identify the worst faults for each individual is to
at generation 85 with that of the (cid:12)rst completely-tolerant
test them with each fault in turn, there can be no short-
consensus whicharises atgeneration204. Thecriterion for
cut. In practice, though, after the (cid:12)rst few generations
‘satisfactoryperformance’wasforthe real robottodisplay
the individuals are mostly similar and the population as
what would reasonably be called wall-avoidingbehaviour,
a whole changes gradually over time. These facts can be
and corresponds to a (cid:12)tness score of (cid:21)1:0.
usedinpredictingwhichfaultsarethemostseriouswithout
Thiscrudeapproachhasexploitedthesimilaritybetween
having to test every individualwith every fault.
individuals in the population by predicting that a single
We now apply these ideas to the robot controller. First,
fault will be the most serious one for all individuals at a
the wall-avoiderwas evolved as before, but this timeusing
a population size of 50. After 85 generations the GA had 3
IftheGAwaslefttorun,thenthesecompletely-tolerantsolutions
stabilisedatagoodsolution. Thenthe consensus sequence would be lost again as the GA concentratedentirely on improving
wasgenerated: thegenotypeformedby,foreachlocus,tak- performanceinthepresenceofthecurrentmostseriousfault|even
if that performance was already satisfactory. No claims are made
ingwhichever ofthevaluesf0,1gwasmostcommoninthe regardingthe generalityand reliabilityof this particularalgorithm
populationatthatposition. Therobotcontrollercodedfor usedhereforillustrativepurposes.
The 32
adverse
SSA
faults.
85 135 185 235
Generations
Fig.10. Theevolutionoffaulttolerance:resultsoftheexhaustivetestoverallpossibleadverseSSAfaultsmadeontheconsensusindividual
of each generation. The darker a spot, the more serious the fault. Pure white represents satisfactory performance((cid:12)tness (cid:21) 1:0),
andpureblacktheworstpossibleperformance. At thegenerationsmarkedwitharrows,theconsensusindividualissatisfactoryinthe
presenceofany SSAfault.
Fitness
1.6
target the weak spots, or search using application-speci(cid:12)c
After
1.4 heuristics mayprove more appropriate.
1.2
Satisfactory performance D. Conclusion to Case Study 1
1.0
The DSMrobot controller experiments showed unequiv-
0.8
ocally that removing the constraints of conventional de-
0.6 sign | in this case, the temporal constraints associated
0.4 withthe digitaldesignparadigm|can release greater be-
Before
havioural capabilities from essentially the same electronic
0.2
components. They provided anexampleofevolutionusing
0.0
this freedom to explore beyond the scope of conventional
design: hypotheses H1 and H2 are demonstrated.
32 possible adverse SSA faults
A technique for the evolution of fault-tolerant circuits
was presented. It is not clear that it can scale up to cir-
Fig.11. Faulttoleranceoftheconsensusatgeneration85,andthen cuits with many possible faults, so it may be restricted
after 119 generationsof evolutionin the presenceof faults. In
to small circuits (or subcircuits), and to problems posed
eachcase,thefaultshavebeensortedfromlefttorightinorder
ofseverity. such that there are many satisfactory solutions. Never-
theless, by integrating the nonbehavioural requirement of
fault tolerance with the behaviouralrequirements, a robot
particular generation. This faultwas identi(cid:12)ed by exhaus- controller was evolved that was inherently fault tolerant,
tivelytestingasingle‘average’individual|theconsensus. not relying on the explicit use of spare (redundant) parts
Though this fault-prediction strategy is not exact, it had as is normal[53],[54]. This was possible because the non-
thedesirede(cid:11)ectofcatalysingtheevolutionofacompletely behavioural,implementation-oriented,requirement was an
fault-tolerant individual. inherent part of the evolutionary design process, and was
Many other strategies could be used to decide which not deferred to the late stages of a top-down design (cid:13)ow.
faultsanindividualshouldencounterduringitsevaluation:
IV. Case Study 2: Evolving a circuit with
the exampleabove is merely a simpleillustration. If there
minimal constraints
were many possible faults, exhaustive testing of even just
the single consensus individual per generation could take In the previous case-study, some temporal constraints
too long. One suggestion is to co-evolve [51] a population were relaxed, but the general architecture of the system
of faults that concentrates on the weak spots of the target was (cid:12)xed. The next step is to discover whether evolution
population and tracks them over time [49], [6]. Another really can produce circuits looking completely alien to an
potential method is the use of repeated re-evaluations of electronicsdesigner,orwhetherinpracticesuchbizarrecir-
the more successful individuals to build up gradually an cuits are unworkable. As (cid:12)rst moves towards this radical
accurate picture of their performance in the presence of a goal,the evolution of unusual oscillatorcircuits was inves-
set of faults [52]. tigated, both in simulation [37] and using recon(cid:12)gurable
Whatever method is used, it seems that if some way of chips [55]. The latter has been greatly extended and stud-
targeting the most serious weak spots of individuals can iedrigorouslybyHuelsbergenet al. [56];seealsothisissue.
be found, then subjecting the individuals to these faults We now elucidate further by studying another task.
during their (cid:12)tness evaluations can cause the evolution of The electronic device selected for the experiments is re-
systems tolerant to all of the possible faults. It may be con(cid:12)gurable at a very (cid:12)ne grain, so as to imposethe mini-
possible to use an adaptive process such as co-evolutionto mumofarchitecturalconstraints: theXilinxXC6216Field-