Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

134 Pages·2014·2.26 MB·English

by  Dai Zhang

Linko¨pingStudiesinScienceandTechnology
Dissertations,No.1611
Ultra-Low-Power Analog-to-Digital
Converters for Medical Applications
DaiZhang
DivisionofElectronicDevices
DepartmentofElectricalEngineering
Linko¨pingUniversity
SE-58183Linko¨ping,Sweden
Linko¨ping2014
Ultra-Low-PowerAnalog-to-DigitalConvertersforMedicalApplications
Copyright©2014DaiZhang
ISBN978-91-7519-264-2
ISSN0345-7524
PrintedbyLiU-Tryck,Linko¨ping,Sweden,2014
Abstract
Biomedicalsystemsarecommonlyattachedtoorimplantedintohumanbodies,and
poweredbyharvestedenergyorsmallbatteries.Inthesesystems,analog-to-digital
converters(ADCs) are key components as the interface between the analog world
andthedigitaldomain.Conversionofthelowfrequencybioelectricsignalsdoesnot
requirehighspeed,butultra-low-poweroperation.Thiscombinedwiththerequired
conversion accuracy makes the design of such ADCs a major challenge. Among
prevalent ADC architectures, the successive-approximation-register (SAR) ADC
exhibitssignificantlyhighenergyefficiencyduetoitsgoodtrade-offsamongpower
consumption,conversionaccuracy,anddesigncomplexity.Thisthesisexaminesthe
physicallimitationsandinvestigatesthedesignmethodologiesandcircuittechniques
forlow-speedandultra-low-powerSARADCs.
The power consumption of SAR ADC is analyzed and its lower bounds are
formulatedinthethesis.Atlowresolutions,powerisboundedbyminimumfeature
sizes;whileatmediumtohighresolutions,powerisboundedbythermalnoiseand
capacitor mismatch. In order to relax the mismatch requirement on the capacitor
sizingwhilestillensuringenoughlinearityforhighresolution,abottom-upweight
calibration technique is further proposed. It utilizes redundancy generated by a
non-binary-weightedcapacitivenetwork,andmeasurestheactualweightsofmore
significantcapacitorsusinglesssignificantcapacitors.
ThreeSARADCshavebeenimplemented.ThefirstADC,fabricatedina0.13µm
CMOSprocess,achieves9.1ENOBwith53-nWpowerconsumptionat1kS/s.The
main key to achieve the ultra-low-power operation turns out to be the maximal
simplicityintheADCarchitectureandlowtransistorcount.Inaddition,adual-supply
voltageschemeallowstheSARdigitallogictooperateat0.4V,reducingtheoverall
powerconsumptionoftheADCby15%withoutanylossinperformance.Basedon
theunderstandingfromthefirstADCandmotivatedbythepredictedpowerbounds,
the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process
hasbeenfurtherfabricated. Itachievesasubstantial(94%)improvementinpower
consumptionwith3-nWtotalpowerat1kS/sand0.7V.Followingthesameconcept
ofimposingmaximalsimplicityintheADCarchitectureandtakingadvantageofthe
smallerfeaturesize,theultra-low-powerconsumptionisachievedbyamatchedsplit-
iv
arraycapacitiveDAC,abottom-platefull-rangeinput-samplingscheme,alatch-based
SARcontrollogic,andamulti-V designapproach. ThethirdADCfabricatedin
T
65nmCMOSprocesstargetsatahigherresolutionof14bandawiderbandwidthof
5KHz.Itachieves12.5ENOBwith1.98-µWpowerconsumptionat0.8Vand10kS/s.
Toachievethehighresolution,theADCimplementsauniform-geometrynon-binary-
weightedcapacitiveDACandemploysasecondary-bitapproachtodynamicallyshift
decisionlevelsforerrorcorrection.Moreover,acomparatorwithbiascontrolutilizes
theredundancytoreducethepowerconsumption.
Popula¨rvetenskaplig
sammanfattning
Biomedicinskasystemdriverutvecklingenavha¨lsova˚rdenframa˚t. Sa˚danasystem
mo¨jliggo¨r hantering av kroniska sjukdomar, medicinsk diagnos, och o¨vervakning
av va¨lma˚endet utanfo¨r traditionella kliniska miljo¨er, vilket ger ho¨gre livskvalitet
tillenla¨grekostnad. Eftersomdessasystemvanligtvisa¨rmonteradeellerimplant-
erade i ma¨nniskokroppen och drivs av sko¨rdad energi eller sma˚ batterier, sa˚ blir
miniatyriseringochultrala˚geffektfo¨rbrukningkritiskadesignspecifikationer.
Idessasystem,a¨ranalog-till-digitalomvandlare(ADC:er)nyckelkomponenter
somgra¨nssnittetmellandenanalogava¨rldenochdendigitaladoma¨nen. Omvand-
ling av la˚gfrekventa bioelektriska signaler kra¨ver inte ho¨g fart, men ultrala˚g ef-
fektfo¨rbrukning.Dettakombineratmeddenno¨dva¨ndigakonverteringsprecisionengo¨r
konstruktionenavsa˚danaADC:ertillenstorutmaning.Dennaavhandlingutforskar
defysikaliskabegra¨nsningarnasamtunderso¨kerdesignmetodikerochkretstekniker
fo¨rla˚ghastighetsochultrala˚geffektsADC:er.
BlandolikaADCarkitekturer,sa˚ gersuccessivapproximationsregister(SAR)
ADC:npa˚tagligtho¨genergieffektivitetp.g.a.dessbalansmellaneffektfo¨rbrukning,
precision,ochdesignkomplexitet.Effektfo¨rbrukningenavSARADC:era¨ranalyserad
ochdessla¨gregra¨nsa¨rformulerad.Baseratpa˚fo¨rsta˚elsenutifra˚nanalysen,implemen-
terastreSARADC:er.Detva˚fo¨rstaanva¨ndermaximalenkelhetiADCarkitekturen
fo¨rattna˚ultrala˚geffektfo¨rbrukningvidmoderataupplo¨sningar.Dentredjeanva¨nder
redundansochdigitalkalibreringfo¨rattna˚ho¨gupplo¨sningochanva¨ndersamtidigt
biaskontrollteknikerfo¨rattreduceraeffektfo¨rbrukningen.DetreADC:ernafortsa¨tter
na¨rmasigdenteoretiskagra¨nsen.
vi
Acknowledgments
ManypeoplehavesupportedandencouragedmeduringmyyearsasaPhDstudent.I
wouldliketoexpressmydeepestgratitudetothem:
• mysupervisor,ProfessorAtilaAlvandpour,forofferingmetheopportunityto
pursuemypostgraduatestudyhere.Heisextremelysupportiveandhasgiven
meinvaluableadviceandhelpondoingresearchandpaperwriting.
• ProfessoremeritusChristerSvensson.Discussingresearchproblemswithhim
is very enjoyable. I hope that I have learned something out of his unique
analyticalapproach.Christerisstillactiveinresearch,beingagreatrolemodel
thatencouragesustostayhungryandstayfoolish.
• ChristerJanssonforalltheinterestingdiscussionsandinvaluablecommentson
circuitdesign.
• AmeyaBhideforthegreatcollaborationonthefirstchip.Iamalsogratefulto
himforbeingafriendlycompany. LifeasaPhDstudentisfullofstruggling
andself-questioning.Thenit’sgoodtoknowyouarenotalone:)
• PrakashHarikumar.Heisalivedictionary.Ibenefitalotfrombothtechnical
andnon-technicaldiscussionswithhim. Oh,Ialmostforgottosay: Prakash,
pleasedon’tworktooomuch!
• ArtaAlvandpourfordesigningthePCBsofthefirsttwochips,solvingtool-
relatedproblems,andborrowingtestequipmentsfromcompanies.
• TimmySundstro¨mandJonasFritzinfortheirvaluablehelpinresearch.Special
thankstoJonasforallthehelpandencouragingwordsduringmyjobsearch.
• ZhenzhiWuforhelpingmetoestimatethehardwarecostoftheerrorcorrection.
• MartinNielsenLo¨nnforhelpingmetotranslatethepopularscientificsummary.
• AliFazliforthegreatcollaborationonteaching.Bytheway,howisthelifeas
apostdocinUSA?
viii
• DanielSva¨rdforhelpingmetosolveany’unsolvable’computer-relatedprob-
lems.
• TedJohanssonforsharinghisexperienceandforthehelponjobsearch.
• J.JacobWiknerforhistoughgraduatecoursesandinterestingposts.Icollected
onlyafewcreditsfromhiscourses,butIlaughedalotreadinghisposts.
• AnnaFolkessonandMariaHamne´r,whohavebeeninvaluableintheirefforts
tosimplifyalltheadministrativedetails.
• allformerandpresentmembersoftheDivisionofElectronicDevices,espe-
ciallyAminOjani,BehzadMesgarzadeh,DuongQuocTai,FahadQazi,Jerzy
Dabrowski,KairangChen,OmidNajari,andShakeelAhmadforbeingnice
colleaguesandcreatingagreatresearchenvironment.
• allmyfriendsforthetimewespenttogether.
• Yuexian.Alwaysbackmeupandhavedonesomuchforme!
• last but not least: Min for sharing the pleasures and sorrows of life with
me;mymotherYuehuaandgrand-parentsShanfuandMeiguiforgivingme
unconditionalloveandsupport.
Finally,profoundthankstothosenotlistedhereforbringingpleasantmomentsin
mylife.
DaiZhang
Linko¨ping,June2014
Contents
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 ReviewofPower-EfficientADCArchitectures . . . . . . . . . . . . 2
1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 ListofPapers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 ThesisOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 SARADCDesignConsiderations 7
2.1 SamplingCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 ThermalNoise . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 ApertureError . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Switch-InducedError. . . . . . . . . . . . . . . . . . . . . 9
2.1.4 TrackBandwidth . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5 VoltageDroop . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 CapacitiveDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 SingleBinary-WeightedCapacitiveArray . . . . . . . . . . 11
2.2.2 SplitBinary-WeightedCapacitiveArray . . . . . . . . . . . 13
2.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 PreamplificationStage . . . . . . . . . . . . . . . . . . . . 17
2.3.2 DynamicLatch . . . . . . . . . . . . . . . . . . . . . . . . 21
3 SARADCPowerAnalysis 27
3.1 CapacitiveDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Single-PoleAmplifier . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 LatchComparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 SARControlLogic . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 PowerConsumptionBoundsofanEntireADC . . . . . . . . . . . 34
4 Designof10-bit1-kS/sSARADCs 37
4.1 A53-nW9.1-ENOBSARADCin0.13µmCMOSProcess . . . . . 38
4.1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 38
x CONTENTS
4.1.2 ADCArchitecture . . . . . . . . . . . . . . . . . . . . . . 39
4.1.3 CapacitiveDAC . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.4 SwitchDesign . . . . . . . . . . . . . . . . . . . . . . . . 42
4.1.5 DynamicLatchComparator . . . . . . . . . . . . . . . . . 44
4.1.6 SARControlLogic . . . . . . . . . . . . . . . . . . . . . . 45
4.1.7 MeasurementResults . . . . . . . . . . . . . . . . . . . . . 46
4.2 A3-nW9.1-ENOBSARADCin65nmCMOSProcess . . . . . . . 50
4.2.1 ComparisoninLeakagebetween0.13µmand65nmCMOS
Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.2 ADCArchitecture . . . . . . . . . . . . . . . . . . . . . . 51
4.2.3 CapacitiveDAC . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.4 SwitchDesign . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.5 DynamicLatchComparator . . . . . . . . . . . . . . . . . 56
4.2.6 SARControlLogic . . . . . . . . . . . . . . . . . . . . . . 57
4.2.7 ChipImplementation . . . . . . . . . . . . . . . . . . . . . 58
4.2.8 MeasurementResults . . . . . . . . . . . . . . . . . . . . . 59
5 DigitalCalibrationofCapacitiveDAC 63
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 CapacitorProperty . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.1 CapacitorVoltageDependence . . . . . . . . . . . . . . . . 65
5.2.2 CapacitorTemperatureDependence . . . . . . . . . . . . . 65
5.3 AnalysisofNon-Binary-WeightedDAC . . . . . . . . . . . . . . . 66
5.3.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.2 AccountingforCapacitorVariation . . . . . . . . . . . . . 67
5.3.3 SecondaryBittoTackleOne-SideRedundancy . . . . . . . 68
5.4 Bottom-UpWeightCalibration . . . . . . . . . . . . . . . . . . . . 71
5.4.1 WeightConversion . . . . . . . . . . . . . . . . . . . . . . 72
5.4.2 Bottom-UpWeightCalibration . . . . . . . . . . . . . . . . 73
5.4.3 SimulationResults . . . . . . . . . . . . . . . . . . . . . . 74
6 A14-BitRedundantSARADCin65nmCMOSProcess 79
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 ADCArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3 CircuitImplementation . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.1 CapacitiveDAC . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.3 BiasingCircuit . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.4 SamplingSwitch . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.5 DigitalControlLogic . . . . . . . . . . . . . . . . . . . . . 91
6.4 MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . . . 92