TPS65094x PMIC for Intel Apollo Lake Platform

93 Pages·2017·1.76 MB·English

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TPS65094
SWCS133D–SEPTEMBER2015–REVISEDMAY2019
TPS65094 PMIC for Intel™ Apollo Lake Platform
1 Device Overview
1.1 Features
1
• WideV rangefrom5.6Vto21V BUCK5(V1P24A)for typicalapplications
IN
• Threevariable-outputvoltagesynchronous • ThreeLDO regulatorswithadjustableoutput
Step-downcontrollersWith D-CAP2™Topology voltage
– 5AforBUCK1(VNN),7AforBUCK6(VDDQ), – LDOA1: I2C-Selectableoutputvoltagefrom1.35
and21AforBUCK2(VCCGI)usingexternal Vto3.3Vfor upto200mAofoutputcurrent
FETsfortypicalapplications – LDOA2andLDOA3: I2C-Selectableoutput
– I2CDynamicVoltageScaling(DVS)control voltagefrom0.7Vto1.5Vfor upto600mAof
(0.5Vto1.45Vin10-mVSteps)forBUCK1 and OutputCurrent
BUCK2 • VTTLDO for DDRmemorytermination
– OTP-Programmabledefaultoutputvoltagefor • Threeloadswitcheswithslewratecontrol
BUCK6(VDDQ) – Upto400mAofoutputcurrentwithvoltage
• Threevariable-outputvoltagesynchronous droplessthan1.5% ofnominalinput voltage
Step-downconverterswithdcs-controltopology – R < 96mΩatinput voltageof1.8V
DSON
andI2CDVS capabilities • I2CInterface(deviceaddress0x5E) supports:
– V rangefrom4.5Vto5.5V
IN – Standardmode(100kHz)
– 3AofoutputcurrentforBUCK3(VCCRAM)
– Fastmode(400kHz)
– 2AofoutputcurrentforBUCK4(V1P8A) and
– Fastmodeplus(1MHz)
1.2 Applications
• 2-,3-,or4-Seriescellli-ionbattery-powered • Tablets,Ultrabook™,andnotebookcomputers
products(NVDCorNon-NVDC) • MobilePCsandmobileinternetdevices
• Wall-powereddesigns,particularlyfrom12-V
supply
1.3 Description
The TPS65094 device is a single-chip solution, power-management integrated chip (PMIC) designed
specifically for the latest Intel™ processors targeted for tablets, ultrabooks, notebooks, industrial PCs, and
Internet-of-Things (IOT) applications using 2S, 3S, or 4S Li-Ion battery packs (NVDC or non-NVDC power
architectures), as well as wall-powered applications. The TPS65094 device is used for essential systems
with low-voltage rails merged for the smallest footprint and lowest-cost system-power solution. The
TPS65094 device provides the complete power solution based on the Intel Reference Designs. Six highly
efficient step-down voltage regulators (VRs), a sink or source LDO (VTT), and a load switch are controlled
by power-up sequence logic to provide the proper power rails, sequencing, and protection—including
DDR3 and DDR4 memory power. The two regulators (BUCK1 and BUCK2) support dynamic voltage
scaling (DVS) for maximum efficiency—including support for Connected Standby. The high-frequency VRs
use small inductors and capacitors to achieve a small solution size. An I2C interface allows simple control
byanembeddedcontroller(EC)orbyasystemonchip(SoC).
The PMIC comes in an 8-mm × 8-mm single-row VQFN package with a thermal pad for good thermal
dissipationandeaseofboardrouting.
DeviceInformation(1)
PARTNUMBER PACKAGE BODYSIZE(NOM)
TPS65094 VQFN(64) 8.00mm×8.00mm
(1) Forallavailablepackages,seetheorderableaddendumattheendofthedatasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TPS65094
SWCS133D–SEPTEMBER2015–REVISEDMAY2019 www.ti.com
1.4 Functional Block Diagram
Optional(a)
Required(b) LDO5V
EC PSSMLLPPIC__SSE34NBB LDOA1 1.352L1 0DV.80 O t VomA (3bA1).3 V DRV5V_2_A1 DRV5V_1_6VSEENT DApeBTpfUyalpiuCcilactK:at 1i1ol Vn BDDORRSVOVWHTL1111 VSYS VNN
SLP_S0B Control EN 0.5 VU stoa g1e.4:5 V FBVOUT1
LSDWOAL1S__EENN(b()a) Inputs (D5V AS) PGNDSNS1
ILIM1
THERMTRIPB
V1P8A VSYS
BOOT2
CLK DRVH2
SoC DATA I2C CTRL DeBfUauCltK: 20V SW2 VCCGI
V1P8A VSET DRVL2
EN Typical
Control Application FBVOUT2
Outputs Usage:
IRQB 0.5 V to 1.45 V PGNDSNS2
(DVS)
RPCSMH_RPSWTBROKIInntteerrrnuaplt CNTL 21 A FBGILNIMD22
PROCHOT Events UPT_ BUCK5V
GPO INTERR RTEEGSOTIST CTPTERRLS VSEENT DefaBuU3ltC :A 1K.305 V <PGND_BUCPKV3FLI>NXB333 VCCRAM
BUCK5V
PVIN4
VSYS
BUVCSKY5SV V5ANA Digital Core VSEENT DefBaUu2lC tA: K14.8 V FLBX44 V1P8A
LDO5V LLDDOO53P3 REFSYS nPUC <PGND_BUCK4> BUCK5V
VREF PVIN5
VSEENT DefaBuU2ltC :A 1K.524 V FLBX55 V1P24A
<PGND_BUCK5>
AGND
VSYS
Thermal
monitoring BOOT6
Thermal shutdown DRVH6
VSEENT DDeeBfapUueClnt:Kd Oe6TntP DRSVWL66 VDDQ
7 A FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
EN ILIM½V Ts×Te V_t DLbDyD OOQTP VTTVFTBT VTT
VSET EN VSET EN EN EN EN
0.76 LV0D 0tOo m A1A2.5 V 0.76 LV0D 0tOo m A1A3.5 V LO3A0D0 SmWAA1 LO4A0D0 SmWAB1 LO4A0D0 SmWAB2
LDOA2 PVINLDOA2_A3 LDOA3 PVINSWA1 SWA1 SWB1 PVINSWB1_B2 SWB2
V1P8A(1)
Dashed connections optional. 0.5 V to 3.3 V 0.5 V to 3.3 V(2)
Refer to Pin Attributes for
connection if unused.
((((12ba)))) LDLLPDDDDOORDAA3RL11 31‡$ aROnZW(cid:3)d‡D$ \LOVZP(cid:3)2DD\DQV·R(cid:3)24Q· 0.5 V to 3.3 V SWA1 (1)V1P8U (2)SWB1_2
Copyright © 2016, Texas Instruments Incorporated
Figure1-1.PMICFunctional BlockDiagram
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Table of Contents
1 DeviceOverview......................................... 1 5.14 TimingRequirements............................... 25
.............................................. ...........................
1.1 Features 1 5.15 Switching Characteristics 26
........................................... ..............................
1.2 Applications 1 5.16 Typical Characteristics 27
1.3 Description............................................ 1 6 DetailedDescription................................... 28
............................ ............................................
1.4 FunctionalBlockDiagram 2 6.1 Overview 28
2 Revision History......................................... 3 6.2 FunctionalBlockDiagram........................... 29
3 DeviceOptions........................................... 5 6.3 FeatureDescription................................. 31
..................................... ...........................
3.1 OTPComparison 5 6.4 DeviceFunctionalModes 48
4 PinConfigurationandFunctions..................... 6 6.5 Programming........................................ 48
5 Specifications........................................... 10 6.6 RegisterMaps....................................... 52
5.1 AbsoluteMaximumRatings......................... 10 7 ApplicationandImplementation.................... 72
........................................ ..............................
5.2 ESDRatings 10 7.1 ApplicationInformation 72
............... ..................................
5.3 RecommendedOperatingConditions 11 7.2 TypicalApplication 72
................................. ................
5.4 Thermal Information 11 7.3 SpecificApplicationforTPS650944 81
5.5 ElectricalCharacteristics:TotalCurrent 7.4 Do'sandDon'ts..................................... 82
........................................
Consumption 11 8 PowerSupplyRecommendations.................. 82
5.6 ElectricalCharacteristics:ReferenceandMonitoring 9 Layout.................................................... 83
..............................................
System 12
...................................
......... 9.1 Layout Guidelines 83
5.7 ElectricalCharacteristics:BuckControllers 13
.....................................
9.2 Layout Example 83
5.8 ElectricalCharacteristics:SynchronousBuck
Converters........................................... 17 10 DeviceandDocumentationSupport............... 84
5.9 ElectricalCharacteristics:LDOs.................... 20 10.1 DeviceSupport ..................................... 84
5.10 ElectricalCharacteristics:LoadSwitches........... 24 10.2 DocumentationSupport............................. 84
5.11 DigitalSignals:I2CInterface........................ 25 10.3 ReceivingNotificationofDocumentationUpdates.. 84
..............................
5.12 DigitalInputSignals(LDOLS_EN,SWA1_EN, 10.4 CommunityResources 84
THERMTRIPB,PMICEN,SLP_S3B,SLP_S4B, 10.5 Trademarks.......................................... 84
...........................................
SLP_S0B) 25 .....................
10.6 ElectrostaticDischargeCaution 84
5.13 DigitalOutputSignals(IRQB,RSMRSTB, .............................................
......................... 10.7 Glossary 84
PCH_PWROK, PROCHOT) 25
2 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionC(May2019)toRevisionD Page
• Added"TPS650947"columntoSummaryofTPS65094xOTPDifferencestable........................................... 5
• ChangedTPS650945DEVICEIDregisterto"Dh"andTPS650944DEVICEIDregisterto"Ch"inSummaryof
TPS65094xOTPDifferencestable................................................................................................. 5
• AddedTPS650947settingstoSection6.6...................................................................................... 52
ChangesfromRevisionB(February2017)toRevisionC Page
• ChangedTPS65094xtoTPS65094intitle........................................................................................ 1
• Deletedvariantsfromtopofeachpage ........................................................................................... 1
• Added"BUCK3-5Mode"rowand"TPS650945"columntoSummaryofTPS65094xOTPDifferencestable........... 5
• ChangedthedescriptionoftheVTTFBpininthePinFunctionstable........................................................ 8
• ChangedVSYStoPVINintheefficiencygraphsforBUCK3,BUCK4,andBUCK5intheTypicalCharacteristics
section................................................................................................................................ 27
• AddedtothedescriptionofthedeassertionconditionthatcausesanemergencyshutdownintheEmergency
Shutdownsection................................................................................................................... 47
• AddedTPS650945settingstoSection6.6...................................................................................... 52
• ChangedOCPeventtopowerfaulteventintheOCPbitdescriptionintheOFFONSRCRegisterField
Descriptionstable................................................................................................................... 54
• ChangedsecondreferenceofTPS650940toTPS650944forthebitresetvaluesintheLDOA2VIDRegister
FieldDescriptionsandLDOA3VIDRegisterFieldDescriptionstables....................................................... 62
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• ChangedthebitvaluesoftheLDOA3_SLPVID[0]andLDOA3_VID[0]bitsintheLDOA3VIDRegisterfigure......... 63
ChangesfromRevisionA(June2016)toRevisionB Page
• UpdatedthePROCHOTpindescriptioninthePinFunctionstable............................................................ 9
• ChangedthevaluesforLX3,LX4,LX5from–1Vand7Vto–2Vand8VintheAbsoluteMaximumRatingstable 10
• ChangedtheresetvalueoftheLDOA2VIDregister(LDOA2VID)toOTPdependent.................................... 62
• AddedtheReceivingNotificationofDocumentationUpdatessection....................................................... 84
• ChangedtheElectrostaticDischargeCautionstatement...................................................................... 84
ChangesfromSeptember11,2015toJune2,2016(from*Revision(September2015)toARevision) Page
• ReleasedfulldatasheetasSWCS133AversionfromSWCS130Bversion.................................................. 1
• ChangeddevicestatustoPROD_DATA.......................................................................................... 1
• ChangedV recommendedminimum............................................................................................. 1
IN
• ChangedFeaturestoimprovedescriptionofconverters ....................................................................... 1
• ChangedFeaturestoupto400mAofoutputcurrentforloadswitches...................................................... 1
• ChangedfunctionalblockdiagramtoincludeTPS65094xfamily ............................................................. 2
• ChangedtheFunctionalBlockDiagramtoincludeaninverteronPROCHOTpin........................................... 2
• ChangedPROCHOTBtoPROCHOTthroughoutthedocument............................................................... 6
• Changedminimumabsolute-maximum-ratingvalueforSW1,SW2,andSW6inSection5.1............................ 10
• ChangedVSYSinSection5.3,RecommendedOperatingConditions ...................................................... 11
• DeletednominalvaluefromPVINVTTinSection5.3,RecommendedOperatingConditions ........................... 11
• Deleted(nu=symbolforefficiency) ............................................................................................. 13
• ChangedBUCK1DCoutputvoltagestepsizetoshowfullrangeandbeconsistentinSection5.7 .................... 13
• Changedtypotomatchcorrectdefaultof1VforΔV inSection5.7 ................................................. 13
OUT_TR
• ChangedBUCK2DCoutputvoltagetoshowfullrangeandbeconsistentinSection5.7................................ 14
• ChangedsetconditionforBUCK6forV rangeinSection5.7tomatchBUCK1andBUCK2 ........................ 15
OUT
• UpdatedformattingandaddednewOTPinformationforBUCK6inSection5.7........................................... 15
• UpdatedformattingforBUCK3DCoutputvoltageinSection5.8............................................................ 17
• ChangedDCoutputvoltageformattingforBUCK4inSection5.8 ........................................................... 18
• ChangedmaximumI valueforBUCK4inSection5.8tomatchdevicecapabilities ................................... 18
OUT
• ChangedI andΔV /ΔI forVTTLDOinSection5.9fornewOTPs................................................. 23
OUT OUT OUT
• ChangedtestconditionsforVTTLDOovercurrentprotectioninSection5.9............................................... 23
• ChangedSection5.10toshowSWB1_2R isspecifiedperoutput .................................................... 24
DSON
• Changedf valuesinSection5.15toprovidemorevalues ................................................................. 26
SW
• Changedcurrentto1.9AtomatchSoCrequirementsinTable6-1......................................................... 28
• ChangedBUCK6,LDOA2,LDOA3typicaloutputvoltagerangeto:OTPDependentinTable6-1...................... 28
• ChangedtablenotetoincludeadditionalDDRtypesinTable6-1........................................................... 28
• ChangedPMICFunctionalBlockDiagramtomatchspecificationstable ................................................... 30
• ChangedPROCHOTBtoPROCHOTintheApolloLakePowerMap ....................................................... 30
• ChangedcurrentratingsinApolloLakePowerMap........................................................................... 30
• DeletedSWBxPGfromPGofPCH_PWROKinTable6-2................................................................... 31
• ChangedBUCK1–2toallBUCKsandLDOAsinSection6.3.3.3............................................................ 36
• AddedTable6-5andTable6-6toSection6.3.4.2............................................................................. 38
• AddedmoreDDRvaluestothetablenoteinTable6-7....................................................................... 39
• ChangedSection6.3.5toincludeLDOA1andresetinformation............................................................. 40
• ChangedSection6.6toincludemultipleDDRs................................................................................. 40
• ChangedFigure6-7andFigure6-8toincludealternateSWB1_2Timing.................................................. 42
• ChangedSWB1_2from:V3P3Ato:V1P8UinTable6-10.................................................................... 42
• ChangedVDDQvoltagetoOTPDependentandSWBxtoSWB1_2inTable6-11 ....................................... 44
• UpdatedFigure6-10toincludealternateSWB1_2Timing.................................................................... 45
• ChangedSection6.3.5.5toincludealternateSWB1_2Timing............................................................... 46
• ChangedSection6.3.5.6toincludeTHERMTRIPB ........................................................................... 47
• AddedtheTPS65094xfamilyOTPvaluestoSection6.6..................................................................... 52
• ReplacedVIDvalueswithlinktofullVIDtableinTable6-18andTable6-19.............................................. 55
• UpdatednamingofbitsintheTEMPHOTregister.............................................................................. 71
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3 Device Options
3.1 OTP Comparison
Table3-1summarizesthedifferencesbetweenthevariousTPS65094xfamilyOTPs.
Table3-1.SummaryofTPS65094xOTPDifferences
TPS650940 TPS650941 TPS650942 TPS650944 TPS650945 TPS650947
DDR LPDDR4 LPDDR3 DDR3L LPDDR4 LPDDR4 DDR3L
BUCK6Voltage 1.1V 1.2V 1.35V 1.1V 1.1V 1.35V
VTTDisabled Yes No No Yes Yes No
VTTIOCP(minimum) 0.95A 0.95A 1.8A 1.8A 0.95A 1.8A
SWB1_2controlledby
Yes Yes No Yes Yes No
SLP_S4B(V1P8U)
SWB1_2controlledby
No No Yes No No Yes
SLP_S3B
Pin14Usage LDOLS_EN LDOLS_EN LDOLS_EN SWA1_EN LDOLS_EN LDOLS_EN
LDOA1AlwaysOn No No No Yes No No
LDOA1DefaultVoltage 3.3V 3.3V 3.3V 1.8V 3.3V 3.3V
LDOA2DefaultVoltage 1.2V 1.2V 1.2V 0.7V 1.2V 1.2V
LDOA3DefaultVoltage 1.25V 1.25V 1.25V 0.7V 1.25V 1.25V
PMICENLowForcesReset Yes Yes Yes No Yes Yes
DEVICEIDRegister 8h 29h 1Ah Ch Dh Fh
BUCK3-5Mode Auto Auto Auto Auto ForcedPWM ForcedPWM
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4 Pin Configuration and Functions
RSKPackage
64-PinVQFNWithThermalPad
TopView
3
B A
P _
RI A2
B B B T O
ILIM2 SLP_S4 SLP_S3 SLP_S0 THERM DATA CLK V5ANA LDO5P0 VSYS LDO3P3 VREF AGND LDOA2 PVINLD LDOA3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
FBGND2 1 48 VTTFB
FBVOUT2 2 47 VTT
DRVH2 3 46 PVINVTT
SW2 4 45 ILIM6
BOOT2 5 44 FBVOUT6
PGNDSNS2 6 43 DRVH6
DRVL2 7 42 SW6
DRV5V_2_A1 8 TOP VIEW 41 BOOT6
PGND/Thermal Pad
LDOA1 9 40 PGNDSNS6
LX3 10 39 DRVL6
PVIN3 11 38 DRV5V_1_6
FB3 12 37 DRVL1
PMICEN 13 36 PGNDSNS1
LDOLS_EN or
14 35 BOOT1
SWA1_EN
IRQB 15 34 SW1
RSMRSTB 16 33 DRVH1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 2 5 5 5 4 4 4 O K T 1 1 1 1
SWB NSWB1_B SWB LX PVIN FB FB PVIN LX GP H_PWRO PROCHO FBVOUT ILIM SWA PVINSWA
VI PC
P
NOTE: Thethermalpadmustbeconnectedtothesystempowergroundplane.
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PinFunctions
PIN SUPPLY,OP
I/O VOLTAGE DESCRIPTION
NO. NAME LEVEL
SMPSREGULATORS
RemotenegativefeedbacksenseforBUCK2controller.ConnecttoVCCGIVSS
1 FBGND2 I
SENSEsentfromtheSoCtothePMIC.
RemotepositivefeedbacksenseforBUCK2controller.ConnecttoVCCGIVCC
2 FBVOUT2 I
SENSEsentfromtheSoCtothePMIC.
3 DRVH2 O VSYS+5V High-sidegatedriveroutputforBUCK2controller
4 SW2 I SwitchnodeconnectionforBUCK2controller
BootstrappinforBUCK2controller.Connecta100-nFceramiccapacitorbetween
5 BOOT2 I VSYS+5V
thispinandSW2pin.
PowerGNDconnectionforBUCK2.Connecttogroundterminalofexternallow-
6 PGNDSNS2 I
sideFET.
7 DRVL2 O 5V Low-sidegatedriveroutputforBUCK2controller
5-VsupplytoBUCK2gatedriverandLDOA1.Bypasstogroundwitha2.2-µF
8 DRV5V_2_A1 I 5V
(typical)ceramiccapacitor.ShortedonboardtoLDO5P0pin.
SwitchnodeconnectionforBUCK3converter.Connecttoa0.47-µH(typical)
10 LX3 O
inductorwithlessthan50-mΩDCR.
PowerinputtoBUCK3converter.Bypasstogroundwitha10-µF(typical)ceramic
11 PVIN3 I 5V
capacitor.
RemotefeedbacksenseforBUCK3converter.Connecttopositiveterminalof
12 FB3 I
outputcapacitor.
SwitchnodeconnectionforBUCK5converter.Connecttoa0.47-µH(typical)
20 LX5 O
inductorwithlessthan50-mΩDCR.
PowerinputtoBUCK5converter.Bypasstogroundwitha10-µF(typical)ceramic
21 PVIN5 I 5V
capacitor.
RemotefeedbacksenseforBUCK5converter.Connecttopositiveterminalof
22 FB5 I
outputcapacitor.
RemotefeedbacksenseforBUCK4converter.Connecttopositiveterminalof
23 FB4 I
outputcapacitor.
PowerinputtoBUCK4converter.Bypasstogroundwitha10-µF(typical)ceramic
24 PVIN4 I 5V
capacitor.
SwitchnodeconnectionforBUCK4converter.Connecttoa0.47-µH(typical)
25 LX4 O
inductorwithlessthan50-mΩDCR.
RemotefeedbacksenseforBUCK1controller.ConnecttoVNNVCCSENSEsent
29 FBVOUT1 I
fromtheSoCtothePMIC.
CurrentlimitsetpinforBUCK1controller.Fitaresistorfromthispintogroundto
30 ILIM1 I
setcurrentlimitofexternallow-sideFET.
33 DRVH1 O VSYS+5V High-sidegatedriveroutputforBUCK1controller
34 SW1 I SwitchnodeconnectionforBUCK1controller
BootstrappinforBUCK1controller.Connecta100-nFceramiccapacitorbetween
35 BOOT1 I VSYS+5V
thispinandSW1pin.
PowerGNDconnectionforBUCK1.Connecttogroundterminalofexternallow-
36 PGNDSNS1 I
sideFET.
37 DRVL1 O 5V Low-sidegatedriveroutputforBUCK1controller
5-VsupplytoBUCK1andBUCK6gatedrivers.Bypasstogroundwitha2.2-µF
38 DRV5V_1_6 I 5V
(typical)ceramiccapacitor.ShortedonboardtoLDO5P0pin.
39 DRVL6 O 5V Low-sidegatedriveroutputforBUCK6controller
PowerGNDconnectionforBUCK6.Connecttogroundterminalofexternallow-
40 PGNDSNS6 I
sideFET.
BootstrappinforBUCK6controller.Connecta100-nFceramiccapacitorbetween
41 BOOT6 I VSYS+5V
thispinandSW6pin.
42 SW6 I SwitchnodeconnectionforBUCK6controller
43 DRVH6 O VSYS+5V High-sidegatedriveroutputforBUCK6controller
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PinFunctions (continued)
PIN SUPPLY,OP
I/O VOLTAGE DESCRIPTION
NO. NAME LEVEL
RemotefeedbacksenseforBUCK6controller.Connecttopositiveterminalof
44 FBVOUT6 I
outputcapacitor.
CurrentlimitsetpinforBUCK6controller.Fitaresistorfromthispintogroundto
45 ILIM6 I
setcurrentlimitofexternallow-sideFET.
CurrentlimitsetpinforBUCK2controller.Fitaresistorfromthispintogroundto
64 ILIM2 I
setcurrentlimitofexternallow-sideFET.
LDOandLOADSWITCHES
LDOA1output.Bypasstogroundwitha4.7-µF(typical)ceramiccapacitor.Leave
9 LDOA1 O 1.35–3.3V
floatingwhennotinuse.
0.5–3.3V
OutputofloadswitchB1.Bypasstogroundwitha0.1-µF(typical)ceramic
17 SWB1 O (1.8-V
capacitor.ShortwithSWB2.
Typical)
0.5–3.3V PowersupplytoloadswitchB1andB2.Bypasstogroundwitha1-µF(typical)
18 PVINSWB1_B2 I (1.8-V ceramiccapacitortoimprovetransientperformance.Connecttogroundwhennot
Typical) inuse.
0.5–3.3V
OutputofloadswitchB2.Bypasstogroundwitha0.1-µF(typical)ceramic
19 SWB2 O (1.8-V
capacitor.ShortwithSWB1.Leavefloatingwhennotinuse.
Typical)
OutputofloadswitchA1.Bypasstogroundwitha0.1-µF(typical)ceramic
31 SWA1 O 0.5–3.3V
capacitor.Leavefloatingwhennotinuse.
PowersupplytoloadswitchA1.Bypasstogroundwitha1-µF(typical)ceramic
32 PVINSWA1 I 0.5–3.3V
capacitortoimprovetransientperformance.Connecttogroundwhennotinuse.
PowersupplytoVTTLDO.Bypasstogroundwitha10-µF(minimum)ceramic
46 PVINVTT I VDDQ
capacitor.Connecttogroundwhennotinuse.
OutputofloadVTTLDO.Bypasstogroundwith2×22-µF(minimum)ceramic
47 VTT O VDDQ/2
capacitors.Leavefloatingwhennotinuse.
RemotefeedbacksenseforVTTLDO.Connecttopositiveterminalofoutput
48 VTTFB I VDDQ/2
capacitor.ShorttoGNDwhennotinuse.
OutputofLDOA3.Bypasstogroundwitha4.7-µF(typical)ceramiccapacitor.
49 LDOA3 O 0.7–1.5V
Leavefloatingwhennotinuse.
PowersupplytoLDOA2andLDOA3.Bypasstogroundwitha4.7-µF(typical)
50 PVINLDOA2_A3 I 1.8V
ceramiccapacitor.Connecttogroundwhennotinuse.
OutputofLDOA2.Bypasstogroundwitha4.7-µF(typical)ceramiccapacitor.
51 LDOA2 O 0.7–1.5V
Leavefloatingwhennotinuse.
Outputof3.3-VinternalLDO.Bypasstogroundwitha4.7-µF(typical)ceramic
54 LDO3P3 O 3.3V
capacitor.
Outputof5-VinternalLDOoraninternalswitchthatconnectsthispintoV5ANA.
56 LDO5P0 O 5V
Bypasstogroundwitha4.7-µF(typical)ceramiccapacitor.
External5-VsupplyinputtointernalloadswitchthatconnectsthispintoLDO5P0
57 V5ANA I 5V pin.Bypassthispinwithanoptionalceramiccapacitortoimprovetransient
performance.
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PinFunctions (continued)
PIN SUPPLY,OP
I/O VOLTAGE DESCRIPTION
NO. NAME LEVEL
INTERFACE
PMICcold-bootpin.Atassertionrisingedgeofthesignalofthispinpowerstate
13 PMICEN I
transitionsfromG3toS4/S5.DrivingthepintoLshutsdownallVRs.
EnablepinforLDOA2,LDOA3,andSWA1whenOTPisconfiguredto
LDOLS_EN.EnablepinforjustSWA1whenOTPisconfiguredtoSWA1_EN.
LDOLS_ENor
14 I Resourcesturnonatassertion(H)andturnoffatdeassertion(L)ofthepin.
SWA1_EN
Optionally,whenthepinispulledlow,thehostcanwritetoenablebitsinReg
0xA0–Reg0xA1tocontroltherails.
Open-drainoutputinterruptpin.RefertoSection6.6.3,IRQ:PMICInterrupt
15 IRQB O
Register,fordefinitions.
Open-drainoutputAlways-ON-railPowerGood.Itreflectsavalidstatewhenever
16 RSMRSTB O
VSYSisavailable.
Open-drainoutputcontrolledbyanI2CregisterbitdefinedinSection6.6.26,
26 GPO O GPO_CTRL:GPOControlRegister,bytheuser,whichthencanbeusedasan
enablesignaltoanexternalVR.
Open-drainoutputglobalPowerGood.ItreflectsavalidstatewheneverVSYSis
27 PCH_PWROK O
available.
Optionalopen-drainoutputforindicatingPMICthermalevent.Invertbefore
28 PROCHOT O connectingtoSoCifused,otherwiseleavefloating.Thispinistriggeredwhenany
ofthePMICdietemperaturesensorsdetectstheT temperature.
HOT
58 CLK I I2Cclock
59 DATA I/O I2Cdata
60 THERMTRIPB I ThermalshutdownsignalfromSoC
Powerstatepin.PMICgoesintoConnectedStandbyatfallingedgeandexitsfrom
61 SLP_S0B I
ConnectedStandbyatrisingedge.
Powerstatepin.PMICgoesintoS3atfallingedgeandexitsfromS3,transitions
62 SLP_S3B I
intoS0atrisingedge.
Powerstatepin.PMICgoesintoS4atfallingedgeandexitsfromS4,transitions
63 SLP_S4B I
intoS3atrisingedge.
REFERENCE
Band-gapreferenceoutput.Stabilizeitbyconnectinga100-nF(typical)ceramic
53 VREF O 1.25V
capacitorbetweenthispinandquietground.
Analogground.Donotconnecttothethermalpadgroundontoplayer.Connectto
52 AGND —
groundofVREFcapacitor.
SystemvoltagedetectionandinputtointernalLDOs(3.3Vand5V).Bypassto
55 VSYS I
groundwitha1-µF(typical)ceramiccapacitor.
THERMALPAD
ConnecttoPCBgroundplaneusingmultipleviasforgoodthermalandelectrical
— Thermalpad —
performance.
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5 Specifications
5.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
MIN MAX UNIT
ANALOG
VSYS Inputvoltagefrombattery –0.3 28 V
PVIN3,PVIN4,PVIN5,LDO5P0,DRV5V_1_6,DRV5V_2_A1,DRVL1,DRVL2,DRVL6 –0.3 7 V
V5ANA –0.3 6 V
PGNDSNS1,PGNDSNS2,PGNDSNS6,AGND,FBGND2 –0.3 0.3 V
DRVH1,DRVH2,DRVH6,BOOT1,BOOT2,BOOT6 –0.3 34 V
SW1,SW2,SW6 –5(2) 28 V
LX3,LX4,LX5 –2(3) 8 V
BOOTxtoSWx Differentialvoltage –0.3 5.5 V
VREF,LDO3P3,FBVOUT1,FBVOUT2,FBVOUT6,FB3,FB4,FB5,ILIM1,ILIM2,ILIM6,PVINVTT,
–0.3 3.6 V
VTT,VTTFB,PVINSWA1,SWA1,PVINSWB1_B2,SWB1,SWB2,LDOA1
PVINLDOA2_A3,LDOA2,LDOA3 –0.3 3.3 V
DIGITALIOs
DATA,CLK,PCH_PWROK,RSMRSTB,GPO –0.3 3.6 V
PMICEN,SLP_S4B,SLP_S3B,SLP_S0B,LDOLS_EN,SWA1_EN,THERMTRIPB,IRQB,PROCHOT –0.3 7 V
Storagetemperature,T –40 150 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) Transientforlessthan5ns.
(3) Transientforlessthan20ns.
5.2 ESD Ratings
VALUE UNIT
Electrostatic HumanBodyModel(HBM),perANSI/ESDA/JEDECJS001(1) ±1000
V V
ESD discharge ChargedDeviceModel(CDM),perJESD22-C101(2) ±250
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
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