through-silicon vias, mechanically flexible interconnects, and positive self-alignment

197 Pages·2014·11.02 MB·English

LARGE-SCALE SILICON SYSTEM TECHNOLOGIES:
THROUGH-SILICON VIAS, MECHANICALLY
FLEXIBLE INTERCONNECTS, AND POSITIVE
SELF-ALIGNMENT STRUCTURES
A Dissertation
Presented to
The Academic Faculty
by
Hyung Suk Yang
In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in the
School of Electrical and Computer Engineering
Georgia Institute of Technology
December 2014
Copyright c 2014 by Hyung Suk Yang
�
LARGE-SCALE SILICON SYSTEM TECHNOLOGIES:
THROUGH-SILICON VIAS, MECHANICALLY
FLEXIBLE INTERCONNECTS, AND POSITIVE
SELF-ALIGNMENT STRUCTURES
Approved by:
Dr. Muhannad S. Bakir, Advisor Dr. Je↵rey A. Davis
School of Electrical and Computer School of Electrical and Computer
Engineering Engineering
Georgia Institute of Technology Georgia Institute of Technology
Dr. James D. Meindl Dr. Yogendra Joshi
School of Electrical and Computer George W. Woodru↵ School of
Engineering Mechanical Engineering
Georgia Institute of Technology Georgia Institute of Technology
Dr. Oliver Brand Dr. Hiren D. Thacker
School of Electrical and Computer Netra Systems and Networking Group
Engineering Oracle
Georgia Institute of Technology
Date Approved: July 29, 2014
To my wife,
Kyu Yun Kim,
and my parents,
Sung Sun Park and Seong Sam Yang,
for their unlimited love and support.
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ACKNOWLEDGEMENTS
First and foremost, I want to thank my advisor Dr. Bakir. It is an honor to be his
first Ph.D. graduate, and I consider myself extremely privileged to have worked with
someone who is so passionate about semiconductors research. His vision, energy, and
enthusiasm for research were sources of motivation when I needed the most, and I
am very grateful to have such an exceptional advisor who made my Ph.D. experience
such a gratifying experience.
I am also extremely grateful to the I3DS and the GSI group members, including
Chaoqi Zhang, Hanju Oh, Yue Zhang, Li Zheng, Reza Abbaspour, Muneeb Zia,
Paragkumar Thadesar, Jiun-hong Lai, Jesal Zaveri, Calvin King, and Ashish Dembla.
Countless number of discussions, both research and personal, have greatly enriched
my experience as a graduate student. I would also like to acknowledge Toby Xu and
Jaime Zahorian for the collaboration work involving TSVs and CMUTs.
I would also like to thank the team at Oracle, including Dr. Thacker, Dr. Raj,
Dr. Shubin, Dr. Cunningham, and Dr. Mitchell. The internship at Oracle was
an eye-opening experience, and the team always provided insights during regular
teleconferences that deeply shaped my research. I would like to acknowledge Dr.
Thacker in particular for being a great mentor during my internship and serving as
a member of my Ph.D. committee. Moreover, I would like to thank Oracle for giving
me the permission to use the material from the internship in my dissertation *.
My experimental research would have not been possible if it weren’t for the ex-
tremely capable and professional sta↵ at the Institute for Electronics and Nanotech-
nology (IEN). I have had my fair share of mistakes, which undoubtedly caused many
headaches for the sta↵. I would like to thank every cleanroom sta↵ for educating
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me rather than suspending me. I would like to especially acknowledge Gary Spinner,
Eric Woods, and Vinny Nguyen for answering my very late night and weekend calls.
I would also like to thank my parents, whom I love very dearly. Without their
encouragement, support, patience, and trust, this work would not have been possible.
Last but definitely not least, I want to thank my wife, Kyu Yun, whom I love most
dearly. Her unconditional and endless love hassupported me during the hardest times
in my life. Without her, I could never have finished this academic endeavor.
- James
* The work presented in Chapter 6 was completed when the author was a 2011
visiting summer intern in the Photonics, Interconnects and Packaging group in Oracle
Labs in San Diego and was published in the ECTC 2012 proceedings [17] and is
reproduced as-is in this thesis as Chapter 6 with permission from Oracle.
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TABLE OF CONTENTS
DEDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . iv
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
1 INTRODUCTION AND BACKGROUND . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 A Silicon Interposer . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Multiple Interposers . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Interconnecting Multiple Interposers . . . . . . . . . . . . . . . . . 8
1.2.1 Electrical Modeling Details . . . . . . . . . . . . . . . . . . . 8
1.2.2 Optical Modeling Details . . . . . . . . . . . . . . . . . . . . 8
1.3 Expected Main Contribution . . . . . . . . . . . . . . . . . . . . . 11
1.4 Research Statement . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 Platform Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.1 Flexible Interconnects . . . . . . . . . . . . . . . . . . . . . . 12
1.5.2 Alignment and Nanophotonics . . . . . . . . . . . . . . . . . 13
1.6 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 THROUGH-SILICON VIAS(TSVS)FORSILICON INTERPOSERS
17
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 TSV Resistance and Capacitance . . . . . . . . . . . . . . . . . . . 19
2.2.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 Estimated Electrical Parameters . . . . . . . . . . . . . . . . 22
2.3 Fabrication of TSVs in Thick Wafers . . . . . . . . . . . . . . . . . 23
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2.3.1 Novel TSV Fabrication Process using “Mesh” . . . . . . . . . 26
2.3.2 Mesh for E�cient Seed-layer Formation . . . . . . . . . . . . 28
2.3.3 Two-metal Process to Eliminate CMP Process . . . . . . . . 29
2.3.4 Low-Temperature Side Wall Passivation . . . . . . . . . . . . 29
2.4 Electrical Verification . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4.2 Leakage Current between TSVs . . . . . . . . . . . . . . . . 31
2.5 Capacitive Ultrasonic Micro-machined Transducers . . . . . . . . . 31
2.5.1 CMUT System Background . . . . . . . . . . . . . . . . . . . 33
2.5.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5.3 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.6 Extended Work: Polymer-clad TSVs . . . . . . . . . . . . . . . . . 40
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 MECHANICALLY FLEXIBLE INTERCONNECTS (MFI) . . 46
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2 1st Generation of MFIs: Fabrication and Mechanical Results . . . . 48
3.2.1 MFI Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.2 Fabrication of Curved MFIs . . . . . . . . . . . . . . . . . . 53
3.2.3 Mechanical Compliance FEM and Measurement . . . . . . . 67
3.2.4 Elastic Range of Movement . . . . . . . . . . . . . . . . . . . 69
3.3 2nd Generation of MFIs: Rematable Tip, Mechanical, Electrical Re-
sults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.1 MFI Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.2 Comparison of Designs . . . . . . . . . . . . . . . . . . . . . 73
3.3.3 Pointy Tip Fabrication . . . . . . . . . . . . . . . . . . . . . 77
3.3.4 Electrical Results . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4 POSITIVESELF-ALIGNMENTSTRUCTURESANDINVERTED
PYRAMID PITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.1.1 E↵ect of Misalignment on Pitch . . . . . . . . . . . . . . . . 80
4.1.2 E↵ect of Misalignment on Bandwidth . . . . . . . . . . . . . 81
4.1.3 E↵ect of Misalignment on Coupling E�ciency of I/Os . . . . 81
4.1.4 Cost of Accurate Alignment . . . . . . . . . . . . . . . . . . 83
4.2 Self-alignment Mechanism . . . . . . . . . . . . . . . . . . . . . . . 85
4.3 Other Self-alignment Technologies . . . . . . . . . . . . . . . . . . 86
4.4 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.4.1 Fabrication of Positive Self-alignment Structures (PSAS) . . 87
4.4.2 Inverted Pyramid Pit Structures . . . . . . . . . . . . . . . . 87
4.5 Geometrical Considerations . . . . . . . . . . . . . . . . . . . . . . 88
4.5.1 Approximating PSAS Shape . . . . . . . . . . . . . . . . . . 88
4.5.2 PSAS Diameter, Pit Opening Size, and Gap . . . . . . . . . 90
4.5.3 Relationship between PSAS Radius, Pit Width, and Gap . . 90
4.6 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.6.1 Vernier Patterns for Measuring Misalignment . . . . . . . . . 93
4.6.2 Fabrication of Vernier Patterns . . . . . . . . . . . . . . . . . 95
4.6.3 Factors A↵ecting Alignment Accuracy . . . . . . . . . . . . . 96
4.7 Alignment Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.7.1 Alignment of Silicon to Silicon, Glass, and FR4 . . . . . . . . 96
4.7.2 Alignment of Multiple Layers of Substrates . . . . . . . . . . 100
4.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5 SILICON INTERPOSER TILES AND BRIDGES . . . . . . . . 102
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.2 PSAS Geometry and Fabrication . . . . . . . . . . . . . . . . . . . 102
5.3 MFI Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.4 Interposer Tile Design and Fabrication . . . . . . . . . . . . . . . . 105
5.5 Bridge Design and Fabrication . . . . . . . . . . . . . . . . . . . . 109
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5.6 Interposer Tiles and Silicon Bridges . . . . . . . . . . . . . . . . . . 110
5.6.1 Assembly of Interposer Tiles and Si Bridges . . . . . . . . . . 110
5.6.2 Alignment Accuracy Measurement . . . . . . . . . . . . . . . 116
5.6.3 Electrical Measurements . . . . . . . . . . . . . . . . . . . . 116
5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6 ELASTOMERIC BUMP INTERPOSER FOR PSAS PACKAG-
ING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3 Package Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.4 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.4.2 Dome Fabrication . . . . . . . . . . . . . . . . . . . . . . . . 129
6.4.3 Mold Fabrication . . . . . . . . . . . . . . . . . . . . . . . . 130
6.4.4 Silicone Stamping . . . . . . . . . . . . . . . . . . . . . . . . 132
6.5 Mechanical Characterization . . . . . . . . . . . . . . . . . . . . . . 133
6.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7 SACRIFICIAL PSAS FOR FLIP-CHIP BOND ASSEMBLY . . 136
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.2 Flip-chip Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.3 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.3.1 Flip-chip Bonding . . . . . . . . . . . . . . . . . . . . . . . . 137
7.3.2 Other Self-alignment Techniques . . . . . . . . . . . . . . . . 139
7.4 Sacrificial Self-alignment Technology . . . . . . . . . . . . . . . . . 140
7.4.1 Geometrical Considerations . . . . . . . . . . . . . . . . . . . 140
7.4.2 Assembly Process . . . . . . . . . . . . . . . . . . . . . . . . 142
7.5 Method and Results . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.5.1 Misalignment Correction . . . . . . . . . . . . . . . . . . . . 145
7.5.2 Thermo-compression Assembly and Electrical Connectivity . 147
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7.5.3 PSAS Removal . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8 FUTURE WORKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.1 Silicon Interposer Tiles and Bridges Platform . . . . . . . . . . . . 153
8.1.1 Co-fabrication of PSAS and MFI . . . . . . . . . . . . . . . . 153
8.1.2 Nanophotonics Integration . . . . . . . . . . . . . . . . . . . 154
8.1.3 RF Characterization of Electrical Interconnects . . . . . . . . 154
8.1.4 Micro-fluidic Cooling on Silicon Interposer Tiles . . . . . . . 154
8.1.5 Elongated Pits and PSAS for Thermo-mechanical Compliance 155
8.2 MFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.2.1 MFI Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.2.2 Vertical Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8.3 PSAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
8.3.1 Gap Measurement . . . . . . . . . . . . . . . . . . . . . . . . 159
8.3.2 Alignment Accuracy Measurement Improvement . . . . . . . 159
8.3.3 Metal-based PSAS . . . . . . . . . . . . . . . . . . . . . . . . 160
9 CONCLUSION AND CHAPTER SUMMARIES . . . . . . . . . 163
9.1 Conclusion of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . 163
9.2 Chapter Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . 163
9.2.1 Through-silicon Via (TSV) . . . . . . . . . . . . . . . . . . . 164
9.2.2 Mechanically Flexible Interconnects . . . . . . . . . . . . . . 164
9.2.3 Positive self-alignment Structures . . . . . . . . . . . . . . . 165
9.2.4 Elastomeric Bump Interposer . . . . . . . . . . . . . . . . . . 165
APPENDIX A — DERIVATION OF BENDING PROFILES . . 166
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
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