The design, fabrication, and test of a CMOS operational amplifier

201 Pages·2016·7.4 MB·English

by  Edward P. Sayre

Rochester Institute of Technology
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Theses Thesis/Dissertation Collections
11-1-1990
The design, fabrication, and test of a CMOS
operational amplifier
Edward P. Sayre
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Sayre, Edward P., "The design, fabrication, and test of a CMOS operational amplifier" (1990). Thesis. Rochester Institute of
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The Design, Fabrication, and Test
of a
CMOS Operational Amplifier
by
Edward P. Sayre III
A Thesis submitted
in
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of the
Requirements for the Degree of
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Electrical Engineering
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Department of Electrical Engineering
College of Engineering
Rochester Institute of Technology
Rochester, New York
November, 1990
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Table of Contents
Chapter 1 Introduction 1
Chapter 2 Design Derivation 5
2.0 Introduction 5
2.1 Differential Amplifier 5
2.1.1 Large Signal Analysis 6
2.1.2 Small Signal Analysis 9
Differential Mode 1 1
-2.1.3
2.1.4 Common Mode 1 4
2.1.5 Frequency Response 1 9
2.2 Output Stage 24
2.2.1 Small signal analysis 25
2.2.2 Frequency Response 28
2.4 Voltage Bias Circuitry 30
Chapter 3 Design Realization 34
3.0 Introduction 34
3.1 Small Signal Gain 34
3.2 Output Resistance 38
3.3 Frequency Response and compensation 39
3.4 Device Sizing 41
3.4.1 Operational Amplifier specification 41
3.5 Simulated Results 49
3.5.1 Input offset voltage 49
3.5.2 DC Mode gain simulations 50
3.5.3 Input Common Mode Range 53
3.5.4 Input and Output Resistance 55
3.6 Frequency Response 56
3.7 Comparison of results 63
3.8 Layout 64
Chapter 4 Processing 67
4.0 Introduction 67
4.1 Process 67
4.2 Results 72
4.2.1 Field Adjust Implant 72
4.2.2 Polysilicon Doping 74
4.2.3 Phosphorous D/S doping 75
4.2.4 Photo resist scumming 76
4.2.5 Non uniform Spin on glass 77
4.2.6 Large leakage currents 78
4.3 Process results 78
Chapter 5 Testing 80
5.0 Introduction 80
5.1 Testing 80
5.1 DC conditions 8 1
.1
5.1.2 Input Offset Voltage 81
5.1.3 Input Common Mode Range 82
5.1.4 Common Mode Gain 83
5.1 Power dissipation 84
.5
5.1 OutputVoltage Range 85
.6
5.2 Frequency Response 85
5.2.1 Demonstration 88
5.3 Individual stages 9 0
5.4 Common Circuits 9 1
5.4.1 Integrator 92
5.4.2 Differentiator 95
5.4.3 Gain Stages 9 7
5.5 Summary 102
Chapter 6 Conclusions 1 03
Chapter 1 Introduction
The topic of this thesis is the design, fabrication, and testing
of a CMOS operational Amplifier. This Operational Amplifier was
first realized as a class design project for Advanced Analog IC
design. Specifications for the device performance were determined
by Dr. Fuller and Edward Sayre to enable the op-amp to be
incorporated into a larger more complex design. The specifications
of the operational amplifier were made to enable design integration
into an amplifier which would operate in the audio frequency range.
The main constraints placed on the design of the op-amp were low
power consumption and a relatively moderate gain.
The following four chapters will discuss the design of the
operational amplifier, (chapters 2 and 3), the fabrication of the op-
amp, (chapter 4), and the testing of the op-amp, (chapter 5). Chapter
2 will deal with the initial design approach deriving pertinent
equations for the different modes of operation of the individual
stages of the op-amp. The design approach of the operational
amplifier divides the op-amp into its components enabling the
circuit derivation to be easily simplified into a manageable solution.
The equations derived in chapter 2 for the different modes of
operation of each stage, differential pair and output stage, will be
presented in both small signal parameters as well as process and
device parameters. Large and small signal analysis will be
performed on the op-amp to insure compliance with the
specifications also to determine the robustness of the design.
The frequency analysis of the operational amplifier will prove
that the system can be represented as a first order system. The
parasitic capacitors of the differential and output stages dictate
the frequency response of the devices without any compensation
capacitances. Chapter 2 will demonstrate that for a compensated
system the singularities introduced by the parasitic capacitors can
be ignored enabling us to model it as a first order system. The
derivation of each stage's frequency transfer function will be able
to be utilized to determine the full transfer function of the
operational amplifier, in chapter 3, since it is a linear system.
Chapter 3 will integrate the individual sections of the op-amp,
discussed in chapter 2, into the whole CMOS operational amplifier.
The investigations of the various modes of operation derived in
chapter 2 for the particular stages of the amplifier are completed to
a final system level which will describe the operation and
performance of the op-amp system. A compensation scheme will be
implemented to achieve the desired frequency response for the
system. The frequency response of the uncompensated operational
amplifier will be compared to the compensated system. Thus
demonstrating the need of compensation.
In Chapter 3 the actual device sizes will be determine from
the performance specifications along with the process parameters.
These value are substituted into the equations derived in chapter 2
and previously in chapter 3. Simulation's of the op-amp are
performed using the S.P.I.C.E simulation tool. Both the large signal,
DC, and small signal, AC, parameters will be evaluated. The models
used in the simulation are either extracted from process
simulations, expected process data, or researched values. The
simulations of the large signal behavior of the op-amp will
demonstrate the ability of the design to meet the DC performance
criteria. The AC data will show that the operational amplifier can
be modeled as a first order system over the frequencies of
operation. The frequency response of the the op-amp will be
evaluated to determine the robustness of the system for closed loop
applications from the open loop characteristics.
The layout of the CMOS operational amplifier is the final
section of chapter 3. The CMOS op-amp is layed out for a Pwell
CMOS process with both the VAX resident Integrated Circuit Editor,
I.C.E., and with Chipgraph, on the Apollo workstations, written by
Mentor Graphics. The operational amplifier is to be layed out as a
whole circuit except for the compensation capacitor due to area
constraints of the device die size. The individual stages making up
the op-amp will also be layed out to allow the investigation into
effects or design particularities that my be isolated to one of the
stages.
Chapter 4 will discuss the Pwell CMOS fabrication process
chosen to construct the CMOS operational amplifier. The CMOS
process developed at Rochester Institute of Technology was modeled
after the Berkeley 3u.m Pwell CMOS process developed at the
University of California, Berkeley. The RIT process modifies the
Berkeley process to suit the manufacturing facilities of the
Microelectronic Engineering fabrication laboratory. A description of
the pertinent processing steps along with the processing
difficulties and modifications experienced are include in chapter 4.