The characterization and model optimization of an analog integrated circuit standard cell library.

171 Pages·2016·9.94 MB·English

by  Mallika Gopinath 1977-

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Electronic Theses and Dissertations
12-2004
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Mallika Gopinath 1977-
University of Louisville
Follow this and additional works at: https://ir.library.louisville.edu/etd
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Gopinath, Mallika 1977-, "The characterization and model optimization of an analog integrated circuit
standard cell library." (2004). Electronic Theses and Dissertations. Paper 518.
https://doi.org/10.18297/etd/518
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THE CHARACTERIZATION AND MODEL OPTIMIZATION OF AN ANALOG INTEGRATED
CIRCUIT STANDARD CELL LIBRARY
By
Mallika Gopinath
B.E., Manipallnstitute of Technology, 1999
A Thesis
Submitted to the Faculty of the
Graduate School of the University of Louisville
In Partial Fulfillment of the Requirements
For the Degree of
Master of Science
Department of Electrical and Computer Engineering
University of Louisville
Louisville, Kentucky
December 2004
THE CHARACTERIZATION AND MODEL OPTIMIZATION OF AN ANALOG INTEGRATED
CIRCUIT STANDARD CELL LIBRARY
By
Mallika Gopinath
B.E., Manipal Institute of Technology, India, 1999
A Thesis Approved on
December 16,2004
By the following Thesis Committee:
Dr. John F. Naber, Thesis Director
Dr. Kevin M. Walsh
Dr. Robert S. Keynton
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ACKNOWLEDGEMENTS
I would like to take this opportunity to thank my thesis advisor, Dr. John. F. Naber, for his
guidance and patience. I am also thankful to the other committee members Dr. Kevin M. Walsh
and Dr. Robert S. Keynton for their comments and critiques. I would also like to thank Mr. Doug
Jackson for all his technical assistance and support in making this thesis a success. Thanks are
also due to Mr. Larry Cassady for his HPVee programs, which helped in the testing of the circuits.
I am grateful to Mr. Tom Carroll for providing the lab equipment and for the lab facility.
I extend my gratitude to my parents, Dr. K. Gopinath and Mrs. Padmini Gopinath for
believing in my endeavors and encouraging me. Finally, I extend my utmost thanks to my
husband, Dr. K Arun Kumar for being supportive, understanding and encouraging me through the
hard and trying times of this thesis.
III
ABSTRACT
THE CHARACTERIZATION AND MODEL OPTIMIZATION OF AN ANALOG INTEGRATED
CIRCUIT STANDARD CELL LIBRARY
Mallika Gopinath
December 16, 2004
Since the beginning of the VLSI era, various technologies have been adopted for
developing the design and characterization of analog circuits. For robust design, the influences of
the process parameter variations have been considered over the circuit simulation. Previous
studies in this field concentrated more on the physical dimensions such as the width, length, area
and perimeter as well as the threshold voltage of the device.
The focus of this thesis was to characterize the performance of an analog IC standard
cell library as well as optimize the simulation models. The circuits include NMOS FETs (n-channel
metal-oxide semiconductor field-effect transistor), PMOS FETs (p-channel metal-oxide
semiconductor field-effect transistor), poly resistors, current mirrors, comparators, bias
generators, voltage references, op-amps, and voltage regulators. The spice model used for
simulation was the BSIM3 (Berkeley Simulator version 3) model.
Tanner Research designed the majority of the standard cells evaluated. These cells were
fabricated in the AMI 1.5-um CMOS process using the MOSIS service. The ICs (Integrated
Circuits) have been developed using software from Tanner Research namely, the schematic
editor, S-Edit; layout editor, L-Edit and simulated using T-Spice (Tanner version of Spice). The
simulations carried out on the circuits using the optimized model exhibited an overall performance
improvement over the unoptimized model. Based on these simulations, numerous plots and
tables are presented and the data was discussed in terms of the output characteristics. There
was a noticeable improvement in the accuracy of 60.44 % for the PMOS FET and17.25% for the
IV
NMOS FET with the optimized model. The DC (direct current) fit using the optimized model over
the unoptimized model showed an improvement of 2.17% (Voltage reference), 1-24% (Bias
Generator), 2% (N-Current mirror), 5% (P-Current mirror), 11-30% (Analog Buffer) and 1.74%
(Op-Amp).
v
TABLE OF CONTENTS
PAGE
ACKNOWLEDGEMENTS ................................................................................................................ iii
ABSTRACT ..................................................................................................................................... iv
LIST OF TABLES ........................................................................................................................... viii
LIST OF FIGURES ........................................................................................................................... x
CHAPTER
1. INTRODUCTION ................................................................................................................. 1
1.1 Background ............................................................................................................. 1
1.2 Literature Review .................................................................................................... 1
1.3 Purpose of Study .................................................................................................... 3
2. DESIGN AND THEORY ...................................................................................................... 4
2.1 MOSFET ................................................................................................................ 5
2.1.1 MOSFET Operation ..................................................................................... 6
2.1.2 Design Calculation for FETs ......................................................................... 7
2.2 Poly Resistors ......................................................................................................... 9
2.3 Voltage Reference ................................................................................................ 11
2.4 Bias Generator ..................................................................................................... 12
2.5 Current Mirror ...................................................................................................... 13
2.6 Analog Buffer ....................................................................................................... 14
2.7 Comparator ........................................................................................................... 16
2.8 Op-Amp ................................................................................................................ 19
2.9 Adjustable Voltage Regulator ............................................................................... 21
3. METHODS ........................................................................................................................ 23
3.1 Software Tools ..................................................................................................... 23
3.2 Measurement Techniques .................................................................................... 24
3.2.1 Automated Method ...................................................................................... 24
3.2.2 Manual Method ........................................................................................... 24
3.3 Design Methodology for FETs .............................................................................. 27
3.4 Modeling of FETs .................................................................................................. 30
4. RESULTS AND DISCUSSIONS ....................................................................................... 36
4.1 MOSFETs ............................................................................................................. 36
4.2 Poly Resistors ....................................................................................................... 51
4.3 Voltage Reference ................................................................................................ 54
4.4 Bias Generator ...................................................................................................... 55
4.5 Current Mirror ....................................................................................................... 56
4.6 Analog Buffer ........................................................................................................ 58
4.7 Comparator ........................................................................................................... 61
4.8 Op-Amp ................................................................................................................ 63
4.9 Adjustable Voltage Regulator ............................................................................... 66
5. CONCLUSIONS AND FUTURE WORK ........................................................................... 70
VI
REFERENCES ............................................................................................................................... 72
APPENDICES ................................................................................................................................ 74
(A) S-Edit Getting Started Manual .................................................................................... 74
(8) T -Spice Getting Started Manual ....................................... : .......................................... 77
(C) 8SIM3 Models ............................................................................................................. 81
(D) MOSFET Tables ........................................................................................................ 131
CURRICULUM ViTAE .................................................................................................................. 159
VII
LIST OF TABLES
TABLE PAGE
1. Transistor Dimensions ........................................................................................................ 8
2. Unoptimized and Optimized data using Percentage Error Method for 24x02um
NMOS FETs ...................................................................................................................... 37
3. Unoptimized and Optimized data using Average Error Current Method for 24x02um
NMOS FETs ...................................................................................................................... 38
4. Unoptimized and Optimized data using Percentage Error Method for 24x02um
PMOS FETs ...................................................................................................................... 39
5. Unoptimized and Optimized data using average error current method for
24x02um PMOS FET ........................................................................................................ 40
6. Scalability data for NMOS FETs ....................................................................................... 42
7. Scalability data for PMOS FETs ........................................................................................ 44
8. Repeatability data for 24x02 um NMOS FETs .................................................................. 45
9. Repeatability data for 24x02 um PMOS FETs .................................................................. 46
10. Resistor Calculation .......................................................................................................... 51
11. Voltage Reference Characteristics .................................................................................... 55
12. Bias Generator Characteristics ......................................................................................... 55
13. N-Current Mirror Characteristics for 2-18-03 Mask Set .................................................... 56
14. N-Current Mirror Characteristics for 9-15-03 Mask Set .................................................... 57
15. P-Current Mirror Characteristics for 2-18-03 Mask SeL ................................................... 57
16. P-Current Mirror Characteristics for 9-15-03 Mask SeL ................................................... 58
17. DC Characteristics of Analog Buffer ................................................................................. 59
18. AC Buffer Characteristics of Analog Buffer ....................................................................... 60
V1 11
19. Buffer Load Test ................................................................................................................ 61
20. Comparator Output Characteristics ................................................................................... 62
21. Comparator Output Characteristics with Different Supply Voltages ................................. 62
22. Inverting op-amp AC Characteristics ................................................................................ 64
23. Nonlnverting op-amp AC Characteristics .......................................................................... 65
24. Inverting op-amp Load Test .............................................................................................. 66
25. Regulator Load Test at Vin=5V for Vout=3.3V .................................................................. 67
26. Regulator Load Test at Vin=5V for Vout=5V ..................................................................... 67
27. Regulator VDD Characteristics for Vout = 3.3V ................................................................ 68
28. Regulator VDD Characteristics for Vout = 5V ................................................................... 68
IX