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About Technology Scaling 2 - Kavindra Kandpal
The document provides information about short channel effects in MOSFETs for a class on analog and digital VLSI design. It includes two examples calculating power density and frequency scaling between technology nodes. It also discusses limitations of technology scaling such as drain induced barrier lowering, subthreshold leakage, and threshold voltage roll-off. Finally, it covers topics relating to interconnect modeling including transmission line models, capacitance and resistance estimation, and different RC delay models.
Detailed Information
| Author: | ['Ayush Y'] |
|---|---|
| Publication Year: | 2019 |
| Pages: | 17 |
| Language: | English |
| Format: | |
| Price: | FREE |
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