Technology-Independent CMOS Op Amp in Minimum Channel Length

289 Pages·2004·5.07 MB·English

Technology-Independent CMOS Op Amp
in Minimum Channel Length

A Thesis
Presented to
The Academic Faculty

by

Susanta Sengupta

In Partial Fulfillment
of the Requirements for the Degree of
Doctor of Philosophy in the
School of Electrical and Computer Engineering

Georgia Institute of Technology
June 2004

Copyright @ 2004 by Susanta Sengupta
Technology-Independent CMOS Op Amp in Minimum
Channel Length

Approved by:

Dr. Phillip E. Allen, Advisor

Dr. Farrokh Ayazi

Dr. Gabriel A. Rincon-Mora

Dr. Marshall Leach

Dr. Thomas Morley

Date Approved: July 8, 2004
To my wife, Proma, my son, Sidharth, and my parents

ii
ACKNOWLEDGEMENT

I would like to thank my advisor, Dr. P.E. Allen for giving me this research
opportunity. During the course of the research, the discussions and his advice
helped me develop the thought process for the research. Understanding the root
cause of a problem and finding the optimal solution is one of the many things I
learnt from him. His consistent support has been very valuable in this research.
I would also like to thank National Semiconductor Corporation for providing us
with the fabrication resources, especially Patrick O. Farrell, who was of great help
in the fabrication runs.
I would also like to thank my friends Sudipto Chakraborty, Ye Ming Li, Ajay
Kumar, Hyusen Dinc and others for their helpful discussions in the design and
testing phases of the research.
Lastly, I would like to thank my wife, Proma, for her support and patience
throughout my research.

iii
TABLE OF CONTENTS

Dedication iii

Acknowledgement iv

List of Tables x

List of Figures xiv

Summary xxi

Chapter 1 Introduction 1

Chapter 2 Implications of Short Channel Length 5
and Technology Dependence on Circuit Performance

2.1 DC Biasing 7
2.2 Small-signal Gain 12
2.3 Mismatch 14
2.4 Limits on Supply Voltage 20
2.5 Noise 21
2.6 High frequency Performance 26
2.7 Distortion 27
2.8 Summary of Use of Minimum Channel Lengths 28
iv
2.9 Technology-Dependent Circuit Performance 29
2.9.1 Op Amp with Current Mirror Load 31
2.9.2 Cascode Op Amp 34
2.10 Effect of Technology Scaling 37
2.11 L -based Gain Stage with Constant Gain 39
min
2.12 L -based Gain Stage for Maximum Gain 45
min
2.13 Weak Inversion Operation of the MOS device 48
2.14 Summary 53

Chapter 3 CMOS Implementation of the Gain Stages 55
in Minimum Channel Length

3.1 Negative Resistance Circuit 55
3.2 Gain Stage with Negative Resistance 58
and Constant Gain
3.3 Bulk Effects 63
3.4 Common-Mode Feedback (CMFB) Circuit 65
3.5 Gain Stage with Negative Resistance 67
and Maximum Gain

3.6 Bias Circuit 70
3.7 Constant Bias Current Generation 73
3.8 Summary 83

Chapter 4 Two-stage, Miller-Compensated Op Amp 84
with Constant Phase Margin

4.1 Op Amp Compensation 85
4.2 Slew Rate 89
v
4.3 Input Referred Noise 89
4.4 Input Common-Mode Range (ICMR) 93
4.5 Power Supply Rejection Ratio (PSRR) 96
4.6 Simulation Results 98
4.6.1 Simulation Results of Op Amp OP1 99
4.6.2 Simulation Results of OP1 in 0.25 mm 101
CMOS Process

4.6.3 Simulation Results of OP1 in 0.18 mm 106
CMOS Process

4.6.4 Comparison of the Simulation Results 113
of OP1 in Two Different CMOS Processes

4.6.5 Simulation Results of Op Amp OP2 114
4.6.6 Simulation Results of OP2 in 0.25 mm 115
CMOS Process

4.6.7 Simulation Results of OP2 in 0.18 mm 120
CMOS Process

4.6.8 Comparison of the Simulation Results 125
of OP2 in Two Different CMOS Processes

4.7 Measurement Results 127

4.7.1 Measurement Results for 127
Matching of Devices

4.7.2 Bias Current Measurements 133
4.7.3 Measured Results of Op Amp OP2 138
4.7.4 Measured Results for OP2 in the 0.25 mm 144
CMOS Process

4.7.5 Measured Results for OP2 in the 0.18 mm 153
CMOS Process

vi
4.8 Summary of L -based Design 156
min

Chapter 5 Technology-Independent Op Amp Design 158
with Constant Gain Bandwidth and Phase Margin

5.1 Generation of Technology-Independent g 159
m
5.2 Gain Stage of OP3 165
5.3 Compensation of OP3 167
5.4 Simulation Results 172
5.4.1 Simulation Results of OP3 in the 0.25 mm 172
CMOS Process

5.4.2 Simulation Results of OP3 in the 0.18 mm 177
CMOS Process

5.4.3 Comparison of the Simulation Results 182
of OP3 in Two Different CMOS Processes

5.5 Measurement Results 185

5.5.1 Measured Results of OP3 in the 0.25 mm 186
CMOS Process

5.5.2 Measured Results of OP3 in the 0.18 mm 192
CMOS Process

5.6 Summary 199

Chapter 6 Buffered Op Amps 201
6.1 Current Feedback g Boosted PMOS Source 202
m
Follower with NMOS current mirror sink

6.2 Current Feedback g Boosted PMOS Source 213
m
Follower with Resistor-NMOS sink

vii
6.3 Current Feedback g Boosted Push-Pull 223
m
Source Follower

6.4 Buffered OP2 228

6.4.1 Simulation Results of Buffered OP2 229

6.4.2 Measurement Results of Buffered OP2 231

6.5 Buffered OP3 237

6.5.1 Simulation Results of Buffered OP3 237

6.5.2 Measurement Results of Buffered OP3 239

6.6 Future Work 252

6.7 Summary 254

Chapter 7 Contributions of the Research 255

References 258

viii
LIST OF TABLES

Table 2.1 Component values for the two-stage op amp with 32
current mirror load

Table 2.2 Comparison of the performance of the two-stage 33
op amp with current mirror load two different
CMOS technologies

Table 2.3 Component values for the cascode op amp 35

Table 2.4 Comparison of the performance of the cascode 36
op amp in two different CMOS technologies

Table 2.5 Circuit parameters with technology scaling 37
Table 3.1 Aspect ratios of the transistors of the gain stage 60
with constant gain

Table 3.2 Aspect ratios of the transistors of the gain stage 68
with maximum gain

Table 3.3 Aspect ratios of the transistors in the bias current 75
generation circuit

Table 4.1 Change in the bias currents of different transistors 95
with an increase in the input common-mode voltage

Table 4.2 Change in the bias currents of different transistors 95
with a decrease in the input common-mode voltage

Table 4.3 Simulated performance of OP1 in the 101
0.25 mm CMOS process

Table 4.4 Simulated performance of OP1 in the 106
0.18 mm CMOS process

Table 4.5 Comparison of the simulated performance of OP1 111
in two different CMOS processes
ix