Techniques for Low-Power High-Performance ADCs Sunghyuk Lee

133 Pages·2014·13.46 MB·English

Techniques for Low-Power High-Performance
ADCs
by
MAASSACHUSETT NS~~iW
Sunghyuk Lee O)F TEHNOLOGY
B.S., Electrical Engineering APR 10 2014
Seoul National University (2005)
UBRARIES
S.M., Electrical Engineering and Computer Science
Massachusetts Institute of Technology (2010)
Submitted to the Department of Electrical Engineering and
Computer Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
February 2014
@ Massachusetts Institute of Technology 2014. All rights reserved.
Author ..
..................................................................
Department of Electrical Engineering and Computer Science
January 31, 2014
Certified by.
Anantha P. Chandrakasan
Professor
Thesis Supervisor
Certified by...
Hae-Seung Lee
Professor
Thesis Supervisor
Accepted by... ........... .. ....
...e.slfie A . K olodziejski
Chair, Department Committee on Graduate Students
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Techniques for Low-Power High-Performance ADCs
by
Sunghyuk Lee
Submitted to the Department of Electrical Engineering and Computer Science
on January 31, 2014, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
Abstract
Analog-to-digital converters (ADCs) are essential building blocks in many electronic
systems which require digital signal processing and storage of analog signals. Tradi-
tionally, ADCs are considered a power hungry circuit. This thesis investigates ADC
design techniques to achieve high-performance with low power consumption.
Two designs are demonst rated. The first design is a voltage scalable zero-crossing
based pipelined ADC. The zero-crossing based circuit technique is modified and op-
timized to improve the limited ADC resolution in nano-scaled CMOS technology.
The proposed unidirectional charge transfer scheme allows faster and more energy
efficient operation by eliminating unnecessary charging and discharging of the capac-
itors. Furthermore, the reduced transient disturbance at the beginning of the fine
charge transfer phase improves the accuracy of operation. Power supply scaling en-
hances power efficiency at low sampling rates much like in digital circuits and widens
the conversion frequency range where the ADC operates with highest efficiency.
The second design is a high speed time-interleaved (TI) SAR ADC with back-
ground timing-skew calibration. A time-interleaved structure is employed to improve
the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used
for each channel to make good use of device scaling. The proposed ADC architecture
incorporates a flash ADC operating at the full sampling rate of the TI ADC. The
flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the
full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output
is also used as the timing reference to estimate the timing-skew of the SAR ADCs.
Thesis Supervisor: Anantha P. Chandrakasan
Title: Professor
Thesis Supervisor: Hae-Seung Lee
Title: Professor
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Acknowledgments
During my time at MIT, I have encountered many people that have helped and
supported me in completing this research and I would like to thank them here.
I would like to deeply thank my advisors, Professor Anantha Chandrakasan and
Professor Hae-Seung Lee. It has been a tremendous privilege to work with them.
Their technical guidance and constant encouragement has allowed me to complete
my research successfully. Not only in technical point of view but also in many other
aspects, I will greatly benefit from all the experiences that I had with them in the
future. I believe that the best and luckiest decision I made at MIT was having them
as my advisors.
I would also like to thank Professor Duane Boning for being on my thesis com-
mittee. He has given me a lot of very useful comments and suggestions to improve
my thesis.
I had chance to work with Professor Charlie Sodini, Kailiang Chen, and Bonnie
Lam for ultrasound project. It was a great experience for me to explorer new areas
and share ideas. Also, I was able to learn system level design and optimization in
this project.
Jack Chu and SungWon Chung were senior members of my research group. They
patiently answered my questions with their knowledge, experience, and intuitions.
Jack provide many reference papers, shared his design, and allowed me to watch
his measurement process. Thanks to his help, I was able to build my skill quickly.
SungWon is an expert on RF/high-speed circuits and I relied heavily on his technical
advice for my second project. He also shared a lot of his custom pcells including pads
and auto routing units with shielding.
Philip Godoy was very helpful with various tasks over the past few years. He
helped my PCB design and programming to control measurement equipments. He
also kindly reviewed my poorly written papers many times and corrected errors in it.
The students in the Lee, Sodini, and Chandrakasan group have been a wonderful
group of people to work with. I will not forget the enjoyable memories with senior
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members (Albert Chow, Matt Guyton, Mariana Markova, Albert Chang, Sushmit
Goswami, Kevin Ryu, Khoa Nguyen, Ivan Nausieda, David He) and junior members
(Daniel Kumar, Hyunho Boo, Doyeon Yoon, Xi Yang, Joohyun Seo, Eric Winoker,
Grant Anderson, Bruno Do Valle, Sabino Pietrangelo, Meggie Delano). Thanks for
making the office a fun and educational place.
Finally, I would like to thank my family members. I really appreciate my wife,
Yunmi Kim, for her patience and understanding. My daughter, Seohyun Emily Lee,
has given me each day of small joys with big smiles. I would also like to thank my
parents for always loving and supporting me unconditionally. I could never have come
this far without them.
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Contents
1 Introduction 19
1.1 M otivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 Thesis Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Zero-Crossing Based Circuit Technique 25
2.1 Zero-Crossing Based Circuits Operation . . . . . . . . . . . . . . . . . 25
2.2 Error Sources of Zero-Crossing Based Circuits . . . . . . . . . . . . . 27
2.3 Prior Work Based on ZCBC . . . . . . . . . . . . . . . . . . . . . . . 29
3 A Voltage Scalable Zero-Crossing Based Pipelined ADC 31
3.1 System Level Improvement . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.1 Unidirectional Two-Phase Charge-Transfer . . . . . . . . . . . 31
3.1.2 Voltage Scaling . . . . . . . . . . . . . . . . . . . . . 34
3.1.3 Reusable Design . . . . . . . . . . . . . . . . . . . 35
3.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . 36
3.2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . 36
3.2.2 Pipelined Stages . . . . . . . . . . . . . . . . . . 37
3.2.3 Sampling Switches . . . . . . . . . . . . . . . . . . 39
3.2.4 Sub-ADC . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.5 Zero-Crossing Detector .. . . . . . . . . . . . . . . . 42
3.2.6 Current Source . . . . . . . . . . . . . . . . . . . . . 46
3.2.7 Multiplying DAC . . . . . . . . . . . . . . . . . . . . 47
3.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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3.4 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.2 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . 53
3.5 Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4 Time-Interleaved ADCs 65
4.1 Principle of Time-Interleaved ADCs . . . . . . . . . . . . . . . . . . . 65
4.2 Issues of Time-Interleaved ADCs . . . . . . . . . . . . . . . . . . . . 68
4.2.1 Offset Mismatches . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2.2 Gain Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2.3 Timing-Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3 Research Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5 A Time-Interleaved SAR ADC with a Background Timing-Skew Cal-
ibration 75
5.1 Block Diagram of the Proposed Time-Interleaved SAR ADC . . . . . 75
5.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.1 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.2 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2.3 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3 Timing-Skew Estimation . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.1 Variance Based Estimation . . . . . . . . . . . . . . . . . . . . 89
5.3.2 Correlation Based Estimation . . . . . . . . . . . . . . . . . . 96
5.3.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4 L ayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.5 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.5.1 Measurement Setup. . . . . . . . . . . . . . . . . . . . . . . . 102
5.5.2 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . 105
5.6 Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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6 Conclusion 121
6.1 Thesis Contribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2 Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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