TAS5782M 30 W Stereo Class-D Amplifier with 96-kHz Processing

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TAS5782M
ZHCSGH3A–MARCH2016–REVISEDJULY2017
TAS5782M 采采用用 96kHz 处处理理架架构构的的 30W 立立体体声声 D 类类放放大大器器
1 特特性性 2 应应用用
• 灵活的音频I/O配置 • 液晶显示屏(LCD)、发光二极管(LED) TV 和多用
1
– 支持I2S、TDM、LJ 和RJ数字输入 途监视器
– 支持采样速率 • 条形音箱、扩展坞和PC音频
– BD 放大器调制 • 无线低音炮、蓝牙扬声器和有源扬声器
– 支持三线制数字音频接口（无需MCLK）
3 说说明明
• 高性能闭环架构（PVDD=12V，R =
SPK
8Ω，SPK_GAIN=20dB） TAS5782M 器件是一款高性能、立体声闭环D类放大
– 闭环= 更少的组件数/更小的解决方案尺寸 器，集成采用96kHz架构的音频处理器。为实现数模
转换，该器件采用了应用Burr-Brown™技术的高性能
– 空闲声道噪声=62μVRMS(A-Wtd)
数模转换器(DAC)该器件仅需两个电源：一个是用于
– 总谐波失真+ 噪声(THD+N)=0.2%(1W/1kHz)
低压电路的DVDD，另一个是用于高压电路的
– 信噪比(SNR)=100dBA-Wtd（以THD+N=
1%为基准） PVDD。它采用标准的I2C通信软件控制端口实现控
制。
• 灵活处理特性
– 15个BiQuad/SmartEQ 输出金属氧化物半导体场效应晶体管(MOSFET) 的
– 适用于X-Over/EQ 的2x5个BiQuad 90mΩr 兼顾散热性能与器件成本，二者相得益
DS(on)
– 三波段高级动态范围压缩(DRC)+ 自动增益限 彰。此外，该器件采用耐热增强型48引脚薄型小外形
制(AGL) 尺寸(TSSOP)，在现代消费类电子器件的较高工作环
– 动态均衡和SmartBass 境温度下展现出优异的性能。
– 声场定位技术(SFS)
器器件件信信息息(1)
– 96kHz 处理器采样
• 通信特性 器器件件型型号号 封封装装 封封装装尺尺寸寸（（标标称称值值））
– 通过I2C端口实现软件模式控制 TAS5782M TSSOP(48) 12.50mmx6.10mm
– 两个地址选择引脚– 多达4个器件 (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 兼具稳定性和可靠性
– 时钟误差、直流和短路保护
– 过热和过流保护
空白
简简化化框框图图
10%THD+N时时的的功功率率与与PVDD间间的的关关系系(1)
TAS5782M
80
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5 1100 15 2200 24
Supply Voltage (V)
D002
(1) 在TAS5782MEVM电路板中进行了测试。
1
AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
EnglishDataSheet:SLASEG8
TAS5782M
ZHCSGH3A–MARCH2016–REVISEDJULY2017 www.ti.com.cn
目目录录
1 特特性性.......................................................................... 1 9.1 Overview.................................................................34
2 应应用用.......................................................................... 1 9.2 FunctionalBlockDiagram.......................................34
3 说说明明.......................................................................... 1 9.3 FeatureDescription.................................................35
4 修修订订历历史史记记录录........................................................... 2 9.4 DeviceFunctionalModes........................................56
10 ApplicationandImplementation........................ 59
5 DeviceComparisonTable..................................... 3
10.1 ApplicationInformation..........................................59
6 PinConfigurationandFunctions......................... 4
10.2 TypicalApplications .............................................61
6.1 InternalPinConfigurations........................................6
11 PowerSupplyRecommendations..................... 70
7 Specifications......................................................... 9
11.1 PowerSupplies.....................................................70
7.1 AbsoluteMaximumRatings......................................9
12 Layout................................................................... 72
7.2 ESDRatings..............................................................9
12.1 LayoutGuidelines.................................................72
7.3 RecommendedOperatingConditions.....................10
12.2 LayoutExample....................................................74
7.4 ThermalInformation................................................10
13 RegisterMaps...................................................... 80
7.5 ElectricalCharacteristics.........................................11
7.6 PowerDissipationCharacteristics..........................15 13.1 Registers-Page0................................................80
7.7 MCLKTiming .........................................................20 13.2 Registers-Page1..............................................116
7.8 SerialAudioPortTiming–SlaveMode..................20 14 器器件件和和文文档档支支持持................................................... 120
7.9 SerialAudioPortTiming–MasterMode................21 14.1 器件支持..............................................................120
7.10 I2CBusTiming–Standard...................................21 14.2 接收文档更新通知...............................................120
7.11 I2CBusTiming–Fast...........................................21 14.3 社区资源..............................................................121
7.12 SPK_MUTETiming ..............................................22 14.4 商标.....................................................................121
7.13 TypicalCharacteristics..........................................24 14.5 静电放电警告.......................................................121
8 ParametricMeasurementInformation...............33 14.6 Glossary..............................................................121
9 DetailedDescription............................................ 34 15 机机械械、、封封装装和和可可订订购购信信息息..................................... 121
4 修修订订历历史史记记录录
注：之前版本的页码可能与当前版本有所不同。
ChangesfromOriginal(March2017)toRevisionA Page
• AddedmissingcrossreferencestotheQuickReferenceTable.......................................................................................... 24
• ChangedChangedtheVolumeRampUp/DownStepdefaultvalueto11.......................................................................... 50
• Changed5thbitoftheI2CSlaveAddresstable .................................................................................................................. 54
• AddedDSPBook,Page,andRegisterUpdatesection....................................................................................................... 56
• DeletedPage0Registers0x0A,0x50,0x51,0x52,and0x54............................................................................................. 80
• ChangedthePLLEbittypeofRegister4fromRtoR/W..................................................................................................... 81
• ChangedBitconfigurationofRegister0x14......................................................................................................................... 88
• ChangedPJDVbitinRegister21from5-4to5-0................................................................................................................ 89
• ChangedResetvalueofRegister0x3Dto'00110000'......................................................................................................... 98
• ChangedBitconfigurationofRegister0x5D...................................................................................................................... 112
• DeletedPage1Registers0x05and0x08.......................................................................................................................... 116
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5 Device Comparison Table
DEVICENAME MODULATIONSTYLE PROCESSINGTYPE
100MIPs,FlexibleProcessflow(UsesmixtureofRAMandROM
TAS5782MDCA BDModulation
componentstocreateseveralprocessflows)
50MIPs,HybridFlow(UsesmixtureofRAMandROMcomponentsto
TAS5754MDCA 1SPW(Ternary)
createseveralprocessflows)
50MIPs,HybridFlow(UsesmixtureofRAMandROMcomponentsto
TAS5756MDCA BDModulation
createseveralprocessflows)
TAS5766MDCA BDModulation 50MIPs,Fixed-Function(UsessingleROMimageofprocessflow)
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6 Pin Configuration and Functions
DCAPackage
48-PinTSSOPwithPowerPAD™
TopView
BSTRPA- 1 48 BSTRPB-
SPK_OUTA- 2 47 SPK_OUTB-
PGND 3 46 PGND
SPK_OUTA+ 4 45 SPK_OUTB+
BSTRPA+ 5 44 BSTRPB+
PVDD 6 43 PVDD
PVDD 7 42 PVDD
GVDD_REG 8 41 PVDD
SPK_GAIN/FSW 9 40 SPK_FAULT
AGND 10 39 PGND
SPK_INA- 11 38 SPK_INB-
SPK_INA+ 12 37 SPK_INB+
PowerPADTM
DAC_OUTA 13 36 DAC_OUTB
AVDD 14 35 CPVSS
AGND 15 34 CN
SDA 16 33 GND
SCL 17 32 CP
GPIO0 18 31 CPVDD
RESET 19 30 DVDD
ADR1 20 29 DGND
GPIO2 21 28 DVDD_REG
MCLK 22 27 SPK_MUTE
SCLK 23 26 ADR0
SDIN 24 25 LRCLK/FS
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PinFunctions
PIN TYPE(1) INTERNAL DESCRIPTION
NAME NO. TERMINATION
ADR0 26 DI SetstheLSBoftheI2Caddressto0ifpulledtoGND,to1ifpulledtoDVDD
ADR1 20 DI SetsthesecondLSBoftheI2Caddressto0ifpulledtoGND,to1ifpulledtoDVDD
10
AGND G — Groundreferenceforanalogcircuitry(2)
15
AVDD 14 P Figure2 Powersupplyforinternalanalogcircuitry
ConnectionpointfortheSPK_OUTA–bootstrapcapacitorwhichisusedtocreateapowersupplyfor
BSTRPA– 1 P
thehigh-sidegatedriveforSPK_OUTA–
ConnectionpointfortheSPK_OUTA+bootstrapcapacitorwhichisusedtocreateapowersupplyfor
BSTRPA+ 5 P
thehigh-sidegatedriveforSPK_OUTA+
Figure3
ConnectionpointfortheSPK_OUTB–bootstrapcapacitorwhichisusedtocreateapowersupplyfor
BSTRPB– 48 P
thehigh-sidegatedriveforSPK_OUTB–
ConnectionpointfortheSPK_OUTB+bootstrapcapacitorwhichisusedtocreateapowersupplyfor
BSTRPB+ 44 P
thehigh-sidegatedriveforSPK_OUTB+
CN 34 P Figure14 Negativepinforcapacitorconnectionusedintheline-driverchargepump
CP 32 P Figure13 Positivepinforcapacitorconnectionusedintheline-driverchargepump
CPVDD 31 P Figure2 Powersupplyforchargepumpcircuitry
CPVSS 35 P Figure14 –3.3-VsupplygeneratedbychargepumpfortheDAC
DAC_OUTA 13 AO Single-endedoutputforChannelAoftheDAC
Figure8
DAC_OUTB 36 AO Single-endedoutputforChannelBoftheDAC
DGND 29 G — Groundreferencefordigitalcircuitry.Connectthispintothesystemground.
DVDD 30 P Figure2 Powersupplyfortheinternaldigitalcircuitry
VoltageregulatorderivedfromDVDDsupplyforuseforinternaldigitalcircuitry.Thispinisprovided
DVDD_REG 28 P Figure15 asaconnectionpointforfilteringcapacitorsforthissupplyandmustnotbeusedtopowerany
externalcircuitry.
GND 33 G — Groundpinfordevice.Thispinshouldbeconnectedtothesystemground.
GPIO0 18
DI/O Generalpurposeinput/outputpins(GPIOx).RefertoGPIOregistersforconfiguration.
GPIO2 21
VoltageregulatorderivedfromPVDDsupplytogeneratethevoltagerequiredforthegatedriveof
GVDD_REG 8 P Figure5 outputMOSFETs.Thispinisprovidedasaconnectionpointforfilteringcapacitorsforthissupplyand
mustnotbeusedtopoweranyexternalcircuitry.
Wordselectclockforthedigitalsignalthatisactiveontheserialport'sinputdataline.InI2S,LJ,and
LRCK/FS 25 DI/O RJ,thiscorrespondstotheleftchannelandrightchannelboundary.InTDMmode,thiscorresponds
Figure11 totheframesyncboundary.
MCLK 22 DI Masterclockusedforinternalclocktreeandsub-circuitandstatemachineclocking
3
PGND 39 G — Groundreferenceforpowerdevicecircuitry.Connectthispintothesystemground.
46
6
7
PVDD 41 P Figure1 Powersupplyforinternalpowercircuitry
42
43
RESET 19 DI Figure17 Deviceresetinput.Pulldowntoreset,pulluptoactivatedevice.
SCL 17 DI Figure10 I2Cserialcontrolportclock
SCLK 23 DI/O Figure11 Bitclockforthedigitalsignalthatisactiveontheinputdatalineoftheserialdataport
SDA 16 DI/O Figure9 I2Cserialcontrolportdata
SDIN 24 D1 Figure11 Datalinetotheserialdataport
SPK_INA– 11 AI NegativepinfordifferentialspeakeramplifierinputA
SPK_INA+ 12 AI PositivepinfordifferentialspeakeramplifierinputA
Figure7
SPK_INB– 38 AI NegativepinfordifferentialspeakeramplifierinputB
SPK_INB+ 37 AI PositivepinfordifferentialspeakeramplifierinputB
(1) AI=Analoginput,AO=Analogoutput,DI=DigitalInput,DO=DigitalOutput,DI/O=DigitalBi-directional(inputandoutput),P=
Power,G=Ground(0V)
(2) Thispinshouldbeconnectedtothesystemground.
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PinFunctions (continued)
PIN TYPE(1) INTERNAL DESCRIPTION
NAME NO. TERMINATION
SPK_FAULT 40 DO Figure16 Faultpinwhichispulledlowwhenanovercurrent,overtemperature,orDCdetectfaultoccurs
SPK_GAIN/F
9 AI Figure6 Setsthegainandswitchingfrequencyofthespeakeramplifier,latchedinuponstart-upofthedevice.
REQ
SPK_OUTA– 2 AO NegativepinfordifferentialspeakeramplifieroutputA
SPK_OUTA+ 4 AO PositivepinfordifferentialspeakeramplifieroutputA
Figure4
SPK_OUTB– 47 AO NegativepinfordifferentialspeakeramplifieroutputB
SPK_OUTB+ 45 AO PositivepinfordifferentialspeakeramplifieroutputB
Speakeramplifiermutewhichmustbepulledlow(connectedtoDGND)tomutethedeviceand
SPK_MUTE 27 I Figure12
pulledhigh(connectedtoDVDD)tounmutethedevice.
Providesbothelectricalandthermalconnectionfromthedevicetotheboard.Amatchinggroundpad
PowerPAD — G — mustbeprovidedonthePCBandthedeviceconnectedtoitthroughsolder.Forproperelectrical
operation,thisgroundpadmustbeconnectedtothesystemground.
6.1 Internal Pin Configurations
PVDD DVDD
30 V ESD 3.3 V ESD
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated
Figure1.PVDDPins Figure2.AVDD, DVDDandCPVDDPins
GVDD BSTRPxx PVDD
PVDD
7 V ESD
SPK_OUTxx
SPK_OUTxx
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated
Figure3.BSTRPxxPins Figure4.SPK_OUTxxPins
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Internal Pin Configurations (continued)
GVDD
PVDD
10 (cid:159)(cid:3)
GVDD
10 N(cid:159)(cid:3)
SPK_GAIN/FREQ
7 V ESD
7 V ESD
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated
Figure5.GVDD_REGPin Figure6.SPK_GAIN/FREQPin
AVDD
SPK_INxx
7 V ESD
Gain Switch
CPVSS
DAC_OUTA
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure7.SPK_INxxPins Figure8.DAC_OUTxPins
DVDD DVDD
SDA
SCL
3.3 V 3.3 V
ESD ESD
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated
Figure9.SDAPin Figure10.SCLPin
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Internal Pin Configurations (continued)
DVDD DVDD
MCLK
SPK_MUTE
SCLK
SDIN 3.3 V 3.3 V
ESD
LRCK/FS ESD
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure11.SCLK,MCLK,SDIN,andLRCK/FSPins Figure12.SPK_MUTEPin
CVPDD
GND
CN
CP 3.3 V
ESD
3.3 V CPVSS
ESD
3.3 V
ESD
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated
Figure13.CPPin Figure14.CNandCPVSSPins
DVDD
100 (cid:159)(cid:3)
SPK_FAULT
DVDD_REG
28 V
ESD
1.8 V
ESD
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated
Figure15.DVDD_REGPin Figure16.SPK_FAULTPin
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Internal Pin Configurations (continued)
DVDD
RESET
3.3 V
ESD
Copyright © 2016, Texas Instruments Incorporated
Figure17.RESETPin
7 Specifications
7.1 Absolute Maximum Ratings
Free-airroomtemperature25°C(unlessotherwisenoted)(1)
MIN MAX UNIT
DVDD,AVDD,
Low-voltagedigital,analog,chargepumpsupply –0.3 3.9 V
CPVDD
PVDD PVDDsupply –0.3 30 V
V InputvoltageforSPK_GAIN/FREQandSPK_FAULTpins –0.3 V +0.3 V
I(AmpCtrl) GVDD
V DVDDreferenceddigitalinputs(2) –0.5 V +0.5 V
I(DigIn) DVDD
V Analoginputintospeakeramplifier –0.3 6.3 V
I(SPK_INxx)
V Voltageatspeakeroutputpins –0.3 32 V
I(SPK_OUTxx)
Ambientoperatingtemperature,T –25 85 °C
A
Operatingjunctiontemperature,digitaldie –40 125 °C
T
J
Operatingjunctiontemperature,powerdie –40 165 °C
T Storagetemperature –40 125 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) DVDDreferenceddigitalpinsinclude:ADR0,ADR1,GPIO0,GPIO2,LRCK/FS,MCLK,RESET,SCL,SCLK,SDA,SDIN,and
SPK_MUTE.
7.2 ESD Ratings
VALUE UNIT
Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000
V V
(ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500
(1) JEDECdocumentJEP155statesthat2000-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat500-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
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7.3 Recommended Operating Conditions
Free-airroomtemperature25°C(unlessotherwisenoted)
MIN NOM MAX UNIT
DVDD,AVDD,CPVDD 2.9 3.63
V Powersupplyinputs V
(POWER)
PVDD 4.5 26.4
BTLMode 3 Ω
R Minimumspeakerload
SPK
PBTLMode 2 Ω
V InputlogichighforDVDDreferenceddigitalinputs(1)(2) 0.9×V V V
IH(DigIn) DVDD DVDD
V InputlogiclowforDVDDreferenceddigitalinputs(1)(3) V 0 0.1×V V
IL(DigIn) DVDD DVDD
MinimuminductorvalueinLCfilterundershort-circuit
L 1 4.7 µH
OUT condition
(1) DVDDreferenceddigitalpinsinclude:ADR0,ADR1,GPIO0,GPIO2,LRCK/FS,MCLK,RESET,SCL,SCLK,SDA,SDIN,and
SPK_MUTE.
(2) ThebestpracticefordrivingtheinputpinsoftheTAS5782Mdeviceistopowerthedrivecircuitorpullupresistorfromthesamesupply
whichprovidestheDVDDpowersupply.
(3) ThebestpracticefordrivingtheinputpinsoftheTAS5782Mdevicelowistopullthemdown,eitheractivelyorthroughpulldown
resistorstothesystemground.
7.4 Thermal Information
TAS5782M
DCA(TSSOP)
48PINS
THERMALMETRIC(1) UNIT
JEDEC JEDEC
TAS5782MEVM
STANDARD STANDARD
4-LAYERPCB
2-LAYERPCB 4-LAYERPCB
R Junction-to-ambientthermalresistance 41.8 27.6 19.4 °C/W
θJA
R Junction-to-case(top)thermalresistance 14.4 14.4 14.4 °C/W
θJC(top)
R Junction-to-boardthermalresistance 9.4 9.4 9.4 °C/W
θJB
ψ Junction-to-topcharacterizationparameter 0.6 0.6 2 °C/W
JT
ψ Junction-to-boardcharacterizationparameter 8.1 9.3 4.8 °C/W
JB
R Junction-to-case(bottom)thermalresistance N/A N/A N/A °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report.
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