Synthesizable VHDL Design for FPGAs

161 Pages·2014·7.825 MB·English

by  Eduardo Augusto Bezerra, Djones Vinicius Lettnin (auth.)

Eduardo Augusto Bezerra
Djones Vinicius Lettnin
Synthesizable
VHDL Design
for FPGAs
Synthesizable VHDL Design for FPGAs
Eduardo Augusto Bezerra
Djones Vinicius Lettnin
Synthesizable VHDL
Design for FPGAs
123
Eduardo AugustoBezerra
Djones ViniciusLettnin
Department of Electricaland Electronic Engineering
Universidade Federalde SantaCatarina
Florianópolis,SantaCatarina
Brazil
ISBN 978-3-319-02546-9 ISBN 978-3-319-02547-6 (eBook)
DOI 10.1007/978-3-319-02547-6
SpringerChamHeidelbergNewYorkDordrechtLondon
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(cid:2)SpringerInternationalPublishingSwitzerland2014
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Contents
1 Digital Systems, FPGAs and the Design Flow . . . . . . . . . . . . . . . 1
1.1 Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Field Programmable Gate Array. . . . . . . . . . . . . . . . . . . . . . 3
1.3 FPGA Internal Organization. . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Electronic Design Automation and the FPGA Design Flow. . . 8
1.6 FPGA Devices and Platforms. . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Writing Software for Microprocessors and VHDL
Code for FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.1 Logic Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.2 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 14
2 HDL Based Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 Theoretical Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.1 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.2 Going Beyond . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Hierarchical Design in VHDL . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.1 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Multiplexer and Demultiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1 Theoretical Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.2 Version I: Multiplexer in Structural VHDL. . . . . . . . 63
4.2.3 Version II: Multiplexer in Behavioral VHDL. . . . . . . 67
5 Code Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1 Arrays of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 Seven Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
v
vi Contents
5.3 Encoders and Decoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.4 Designing a Seven Segment Decoder . . . . . . . . . . . . . . . . . . 74
5.5 Case Study: A Simple but Fully Functional Calculator . . . . . . 76
5.6 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6 Sequential Circuits, Latches and Flip-Flops. . . . . . . . . . . . . . . . . 85
6.1 Sequential Circuits in VHDL: The Process Statement. . . . . . . 85
6.2 Describing a D Latch in VHDL. . . . . . . . . . . . . . . . . . . . . . 88
6.3 Describing a D Flip-Flop in VHDL . . . . . . . . . . . . . . . . . . . 91
6.4 Implementing Registers with D Flip-Flops. . . . . . . . . . . . . . . 94
6.5 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7 Synthesis of Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . 99
7.1 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 VHDL Synthesis of Finite State Machines. . . . . . . . . . . . . . . 101
7.3 FSM Case Study: Designing a Counter. . . . . . . . . . . . . . . . . 105
7.4 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.4.1 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 108
8 Using Finite State Machines as Controllers . . . . . . . . . . . . . . . . . 111
8.1 Designing an FSM Based Control Unit. . . . . . . . . . . . . . . . . 111
8.2 Case Study: Designing a Vending Machine Controller . . . . . . 113
8.3 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.3.1 Problem Definition: Calculator with Reduced
Data Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.3.2 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 120
8.3.3 Adding a New Input Register to the Calculator
Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.3.4 Designing an FSM Based Controller
for the Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . 122
9 More on Processes and Registers . . . . . . . . . . . . . . . . . . . . . . . . 127
9.1 Implicit and Explicit Processes. . . . . . . . . . . . . . . . . . . . . . . 127
9.2 Designing a Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.3 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.3.1 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 134
10 Arithmetic Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.1 Half-Adder, Full-Adder, Ripple-Carry Adder. . . . . . . . . . . . . 137
10.2 Laboratory Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
10.2.1 Laboratory Session. . . . . . . . . . . . . . . . . . . . . . . . . 145
Contents vii
11 Writing Synthesizable VHDL Code for FPGAs . . . . . . . . . . . . . . 147
11.1 Synthesis and Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.2 VHDL Semantics for Synthesis . . . . . . . . . . . . . . . . . . . . . . 148
11.3 HDLGen: Automatic Generation of Synthesizable VHDL. . . . 153
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 1
Digital Systems, FPGAs and the Design
Flow
This chapter introduces the target technology used in the laboratory sessions, and
provides astep-by-stepguideforthedesignandsimulation ofadigitalcircuit.At
the end of this chapter, the reader should be able:
• to have a basic understanding of the FPGA technology (internal blocks,
applications);
• to understand the basic logic gates operation;
• to design a logic circuit using a schematic editor tool;
• to simulate and test a digital circuit;
• to understand the basic flow of an Electronic Design Automation (EDA) tool.
1.1 Digital Systems
Digitalsystemsarecomposedoftwobasiccomponents:DatapathandControlUnit.
As shown in Fig. 1.1, the control unit has as its main function the generation of
controlsignalstothedatapathunit(alsoknownas‘‘operationalblock’’).Thecontrol
signals‘‘command’’thedesiredoperationsinthedatapath.Furthermore,thecontrol
unitmayreceivecontrolinputsfromtheexternalenvironment;forinstance,itcan
be a simple ‘‘start’’ or even an operation code (‘‘opcode’’ in microprocessors).
Finally, this unit can also generate one or more output control signals to commu-
nicatewithotherdigitalsystems(e.g.,‘‘done,busrequest,nack’’).
The datapath unit performs operations on data received, usually, from the
external environment. The operations are performed in one or more steps, where
eachsteptakesaclockcycle.Thedatapathgenerates‘‘status’’signals(sometimes
alsocalledas‘‘flags’’)thatareusedbythecontrolblocktodefinethesequenceof
operations to be performed. Examples of datapath blocks include:
• Interconnection network—wires, multiplexers, buses, and tri-state buffers;
• Functional units—adders, subtractors, shifters, multipliers, and Arithmetic and
Logic Unit (ALU);
E.A.BezerraandD.V.Lettnin,SynthesizableVHDLDesignforFPGAs, 1
DOI:10.1007/978-3-319-02547-6_1,
(cid:2)SpringerInternationalPublishingSwitzerland2014
2 1 DigitalSystems,FPGAsandtheDesignFlow
Fig.1.1 Digitalsystem
(adaptedfrom
[ManoKime99])
• Memory elements—registers, and Random Access Memory (RAM).
Thedatapathandcontrolunitsarebasedontwotypesofcircuits:combinational
and sequential circuits.
Combinational circuits have I inputs and O outputs, as shown in Fig. 1.2. In
m n
these circuits the output pins depend only on the values that are presented to the
input pins and each output is defined by a different Boolean logic equation.
A combinational circuit can also be classified according to its application as:
• Interconnectioncircuit—e.g.multiplexers,demultiplexers,encoders,anddecoders;
• Logical and arithmetic circuit—e.g. adders, subtractors, multipliers, shifters,
comparators, and ALUs (circuits that combine more than one arithmetic or
logical modules).
SequentialcircuitshaveI inputsandO outputs.However,inthesecircuitsthe
m n
output pins depend not only on the values that are presented to the input signals
(i.e. m signals), but they depend also on the current state stored in the memory
module, as shown in Fig. 1.3. The number of both next state (i.e. N) and current
j
statesignals(i.e.S)dependontheencodingstyleofaFiniteStateMachine(FSM)
j
states, such as, sequential binary, gray code or one hot.
Fig.1.2 Combinational
circuit
1.2 FieldProgrammableGateArray 3
Fig.1.3 Sequentialcircuit
1.2 Field Programmable Gate Array
The concept behind the Field Programmable Gate Array (FPGA) technology is
better understood through a digital circuit design example.
Problem:
You are asked to design a circuit that implements the following logic function:
fðA;BÞ ¼AANDB
In this circuit, inputs A, B, and output f are all 4 bits wide.
Solution 1: Using a 7408 TTL device (Application-specific Integrated Circuit—
ASIC solution)
The operations to be performed are:
fð1Þ¼Að1ÞANDBð1Þ
fð2Þ¼Að2ÞANDBð2Þ
fð3Þ¼Að3ÞANDBð3Þ
fð4Þ¼Að4ÞANDBð4Þ
The7408TTLdevice,showninFig. 1.4,hasfour1-bitANDgates.Therefore,
a single 7408 chip is sufficient to implement the 4 bits function. In Fig. 1.4, the
Ainputsareconnectedtopins1,4,9and12.TheBinputsareconnectedtopins2,
5,10and13.Thefoutputcanbeobtainedfrompins3,6,8and11.Thechipmust
be placed (soldered) on a printed circuit board (PCB) or protoboard, and all pin
connections should be made, including the power lines (Vcc and GND).
This is a nice solution for the proposed problem, but it has some drawbacks.
TTLisanobsoletetechnology,presentinghigh-energyconsumption,andthechip
itselftakesconsiderablespaceonthePCB.Anotherdrawbackisincaseofchanges