Substrate Noise Coupling in RFICs (Analog Circuits and Signal Processing)

129 Pages·2008·3.64 MB·English

by  Ahmed Helmy

SUBSTRATE NOISECOUPLINGIN RFICS
ANALOGCIRCUITSANDSIGNALPROCESSINGSERIES
ConsultingEditor:MohammedIsmail.OhioStateUniversity
TitlesinSeries:
SUBSTRATENOISECOUPLINGINRFICs
Helmy,Ahmed,Ismail,Mohammed
ISBN:978-1-4020-8165-1
BROADBANDOPTO-ELECTRICALRECEIVERSINSTANDARDCMOS
Hermans,Carolien,Steyaert,Michiel
ISBN:978-1-4020-6221-6
ULTRALOWPOWERCAPACITIVESENSORINTERFACES
Bracke,Wouter,Puers,Robert,VanHoof,Chris
ISBN:978-1-4020-6231-5
LOW-FREQUENCYNOISEINADVANCEDMOSDEVICES
Haartman,Martinv.,O¨stling,Mikael
ISBN-10:1-4020-5909-4
CMOSSINGLECHIPFASTFREQUENCYHOPPINGSYNTHESIZERSFORWIRELESS
MULTI-GIGAHERTZAPPLICATIONS
Bourdi,Taoufik,Kale,Izzet
ISBN:978-14020-5927-8
ANALOGCIRCUITDESIGNTECHNIQUESAT0.5V
Chatterjee,S.,Kinget,P.,Tsividis,Y.,Pun,K.P.
ISBN-10:0-387-69953-8
IQCALIBRATIONTECHNIQUESFORCMOSRADIOTRANCEIVERS
Chen,Sao-Jie,Hsieh,Yong-Hsiang
ISBN-10:1-4020-5082-8
FULL-CHIPNANOMETERROUTINGTECHNIQUES
Ho,Tsung-Yi,Chang,Yao-Wen,Chen,Sao-Jie
ISBN:978-1-4020-6194-3
THEGM/IDDESIGNMETHODOLOGYFORCMOSANALOGLOWPOWER
INTEGRATEDCIRCUITS
Jespers,PaulG.A.
ISBN-10:0-387-47100-6
PRECISIONTEMPERATURESENSORSINCMOSTECHNOLOGY
Pertijs,MichielA.P.,Huijsing,JohanH.
ISBN-10:1-4020-5257-X
CMOSCURRENT-MODECIRCUITSFORDATACOMMUNICATIONS
Yuan,Fei
ISBN:0-387-29758-8
RFPOWERAMPLIFIERSFORMOBILECOMMUNICATIONS
Reynaert,Patrick,Steyaert,Michiel
ISBN:1-4020-5116-6
ADVANCEDDESIGNTECHNIQUESFORRFPOWERAMPLIFIERS
Rudiakova,A.N.,Krizhanovski,V.
ISBN1-4020-4638-3
CMOSCASCADESIGMA-DELTAMODULATORSFORSENSORSANDTELECOM
delR´ıo,R.,Medeiro,F.,Pe´rez-Verdu´,B.,delaRosa,J.M.,Rodr´ıguez-Va´zquez,A.
ISBN1-4020-4775-4
SIGMADELTAA/DCONVERSIONFORSIGNALCONDITIONING
Philips,K.,vanRoermund,A.H.M.
Vol.874,ISBN1-4020-4679-0
CALIBRATIONTECHNIQUESINNYQUISTADCONVERTERS
vanderPloeg,H.,Nauta,B.
Vol.873,ISBN1-4020-4634-0
ADAPTIVETECHNIQUESFORMIXEDSIGNALSYSTEMONCHIP
Fayed,A.,Ismail,M.
Vol.872,ISBN0-387-32154-3
WIDE-BANDWIDTHHIGH-DYNAMICRANGED/ACONVERTERS
Doris,Konstantinos,vanRoermund,Arthur,Leenaerts,Domine
Vol.871ISBN:0-387-30415-0
Substrate Noise Coupling in RFICs
by
AHMED HELMY
OhioStateUniversity,Columbus,OH,USA
and
MOHAMMEDISMAIL
AnalogVLSILab,TheOhioStateUniversity,Columbus,OH,USA
Dr.AhmedHelmy Dr.MohammedIsmail
OhioStateUniversity AnalogVLSILab
Dept.Electrical&Computer TheOhioStateUniversity
Engineering Dept.Electrical&Computer
2015NeilAvenue Engineering
ColumbusOH43210 2015NeilAvenue
USA ColumbusOH43210
[email protected] USA
[email protected]
ISBN:978-1-4020-8165-1 e-ISBN:978-1-4020-8166-8
LibraryofCongressControlNumber:2008922524
(cid:2)c 2008SpringerScience+BusinessMediaB.V.
Nopartofthisworkmaybereproduced,storedinaretrievalsystem,ortransmitted
inanyformorbyanymeans,electronic,mechanical,photocopying,microfilming,recording
orotherwise,withoutwrittenpermissionfromthePublisher,withtheexception
ofanymaterialsuppliedspecificallyforthepurposeofbeingentered
andexecutedonacomputersystem,forexclusiveusebythepurchaserofthework.
Printedonacid-freepaper
9 8 7 6 5 4 3 2 1
springer.com
Thisbookisdedicatedto Yasmin,Zeina, Aly,
OmarandMohammed Ismail’sfamily
Preface
Substrate noise couplingin integratedcircuits(ICs) is the processby whichinter-
ferencesignalsin the formof voltageandcurrentglitchescause parasiticcurrents
toflowinthesiliconsubstratetovariouspartsoftheIC.Thesourceofsuchglitches
andparasiticcurrentscouldbefromtheswitchingnoiseofhighspeeddigitalclocks
on the same chip. In RF and mixed signal ICs the switching noise is coupled to
sensitive analog and RF nodes in the IC causing degradation in performance that
couldseverelyimpacttheyield.Thus,overcomingsubstratecouplingisakeyissue
in successful “system on chip” first-pass integration where RF and mixed signal
blocks, high speed digital I/O interface are integrated with digital signal process-
ing algorithms on the same chip. This is particularly true as we move to sub-90
nanometersystemonchipintegration.
Inthisbookasubstrateawaredesignflowisbuilt,calibratedtosiliconandused
as part of the design and validation flows to uncover and fix substrate coupling
problems in RF ICs. The flow is used to develop a comprehensive RF substrate
noiseisolationdesignguideto beusedbyRF designersduringthe floorplanning,
circuitdesignandvalidationphases. Thiswill allow designersto optimizethe de-
sign, maximize noise isolation and protect sensitive analog/RF blocks from being
degradedbysubstratenoisecoupling.
Several effects of substrate coupling on circuit performance will be identified
andremedieswillbegivenbasedontheproposeddesignguide.Threecasestudies
aredesignedtoanalyzethesubstratecouplingprobleminRFICs.Thecasestudies
aredesignedtograduallyattacktheproblematthedevice(Case1),circuit(Case2)
and system levels (Case 3). At the device level a special emphasis is given to the
designofonchipinductorsasanimportantdeviceintoday’sSOCsystemsandthe
impactofsubstratenoisecouplingontheinductorperformanceischaracterized.An
accuratemodelisdevelopedforabroadbandfitoftheinductorscatteringparameters
toa lumpedmacromodelthatisused inthe systemanalysisofcase study3.This
modelisshowntobescalableandisproventobeaccuratewhenappliedtovarious
frequencybands and inductor geometries. A special emphasis is put on the DFM
effectsthataffectthedesignrobustness.Acircuitlevelcasestudyisdevelopedand
resultsarecomparedtosimulationsandsiliconmeasurementstohighlighttheneed
forsuchaflowbeforesiliconfabrication“tapingout”toensureayieldingpart.In
case study 3 a system level problem is studied on a GSM cellular receiver chain.
vii
viii Preface
Theresultsareusedasademonstrationvehicletodebugandresolveasystemlevel
substratenoisecouplingproblemthatwouldotherwisehavecausedthereceiverto
malfunction, with adverse implication on yield and profit margin for such a high
volumeproduct.
Chapter1introducestheworkandhighlightsthemotivation,objectiveandcon-
tribution.Chapter2discussesthephenomenaofsubstratecoupling.Devicestosub-
strateinterface,noiseinjection,receptionandpropagationareexplainedindetails.
Theindustrystandardalgorithmsusedtomodelthesubstratearestudiedandcom-
pared.Thedesignmethodologyusedtoaccountforandintegratethesubstratemodel
inthedesignflowishighlighted.InChapter3thedesignexperimentsarediscussed,
atestchipisdescribedtogetherwiththede-embeddingtechniqueandmeasurement
procedure. The design flow is then developed to model the substrate and is cali-
bratedtothemeasurementdataandsimulationsvs.measurementsarereportedasa
foundationofadesignflowthatisusedinthenextchapters.InChapter4asubstrate
isolation guide is developed based on two main methodologies. First, circuit and
layout considerations are presented to maximize isolation, namely floor planning
techniques.Supplylinedistributionandgroundrailsarealsodesignedtomaximize
substrateisolation.Secondly,isolationstructuresareintroducedanddesigned.Bias-
ingandsizingofsuchstructuresarediscussed;allarebasedonthecalibrateddesign
environmentdevelopedinChapter3.InChapter5understandingtheimpactofthese
isolationstructuresandthesubstratecharacteristicsisusedtodevelopadesignflow
foronchipspiralinductors.Measurementsandsimulationsarecomparedtovalidate
theflowandvariousflavorsofonchipinductorsaredesignedtofittheneedsofsev-
eralRF applications.A scalable inductormacromodelis developedthatis shown
to be usableto a verygoodaccuracyacrossa widevarietyof inductorgeometries
and frequency bands. DFM effects are studied and their impacts are highlighted
on the inductorperformance.Chapter 6 presentsthreeindustrialcase studies. The
case studies are designed to gradually show the impact of substrate coupling at a
device,acircuitandthenatasystemlevel.Simulationandmeasurementresultsare
shownwithandwithoutapplyingtheisolationtechniquesandresultsarecompared.
Chapter7concludestheworkandproposesfuturework.
ThisbookisintendedforRFandmixedsignaldesignengineers,system-on-chip
designersandprocessengineersaswellasgraduatestudentsandresearchersinthe
fieldsofintegratedcircuitsandsystemsonchipdesignandoptimization.
The work has its roots in the Ph.D. dissertation of the first author, completed
attheAnalogVLSILab,theDepartmentofElectricalandComputerEngineering,
TheOhioStateUniversity.Wewouldliketothankallthosewhoassistedusduring
differentphasesofthisworkincludingourcolleaguesattheAnalogVLSILaband
atIntelCorporation.WealsoliketothanktheSemiconductorResearchCorporation
forpartiallyfundingthiswork.Finally,wewouldliketothankourfamiliesfortheir
helpandsupport.
Columbus,Ohio AhmedHelmy
MohammedIsmail
Contents
1 Introduction ................................................... 1
1.1 MotivationandObjectives ................................... 1
1.2 Contributions .............................................. 5
1.3 BookOrganization.......................................... 5
2 AnalysisofSubstrateNoiseCoupling ............................. 7
2.1 ProcessRegions............................................ 7
2.2 ProcessCrossSections ...................................... 8
2.3 ConnectionofDevicestotheSubstrate......................... 10
2.4 NoiseCouplingMechanism .................................. 12
2.5 SubstrateDopingProfileTradeoffs ............................ 18
2.6 SubstrateModelExtractionintheICDesignFlow ............... 18
2.7 DopingProfileConsiderations................................ 19
2.8 SubstrateModelExtractionKernels ........................... 20
2.9 Conclusion ................................................ 24
3 ExperimentalDatatoCalibratetheDesignFlow ................... 25
3.1 Introduction ............................................... 25
3.2 TheTestChip.............................................. 26
3.3 BaselineIsolation .......................................... 28
3.4 Effectofp-GuardRingonIsolation ........................... 30
3.5 Effectofn-GuardRingonIsolation ........................... 32
3.6 EffectofDeepn-WellonIsolation ............................ 35
3.7 EffectofDeepTrenchonIsolation ............................ 37
3.8 De-embedding ............................................. 38
3.9 Conclusion ................................................ 41
4 DesignGuideforSubstrateNoiseIsolationinRFApplications ....... 43
4.1 Introduction ............................................... 43
4.2 IsolationinLowResistivitySubstrate.......................... 43
4.3 Isolationvs.FrequencyforDifferentIsolationStructures.......... 44
4.4 Effect of Back Plane Connection on the Noise Isolation
inHighResistivitySubstrates ................................ 45
ix
x Contents
4.5 SubstrateContacts:FrontsideorBackside?Both................. 48
4.6 P+GuardRingIsolation .................................... 48
4.7 P+andN+GuardRingsIsolation ............................ 55
4.8 FloorPlanningTechniquestoMinimizeCoupling................ 56
4.9 CircuitTechniquestoMinimizeCoupling ...................... 59
4.10 ActiveGuardRings......................................... 60
4.11 Conclusion ................................................ 60
5 OnChipInductorsDesignFlow .................................. 63
5.1 Introduction ............................................... 63
5.2 IntegratedInductors......................................... 63
5.3 InductorDesignFlow ....................................... 65
5.4 AnalyticalExplorationoftheDesignSpace..................... 65
5.5 InductorModelandSubstrateParasitics........................ 71
5.6 CalibratingtheFieldSolver .................................. 74
5.7 ModelFit ................................................. 75
5.8 DFMEffects............................................... 77
5.9 Conclusion ................................................ 85
6 Case Studies for the Impacts and Remedies of Substrate Noise
Coupling ....................................................... 87
6.1 Introduction ............................................... 87
6.2 SystemLevelCaseStudy .................................... 88
6.3 BlockLevelCaseStudy ..................................... 96
6.4 DeviceLevelCaseStudy ....................................101
6.5 Conclusion ................................................103
7 ConclusionandFutureWork ....................................105
A ScatteringParameters ...........................................107
B MeasurementsSetup ............................................109
Bibliography.......................................................113
Index .............................................................119