STC89C51(52)RC/RD+ series MCU STC89LE51(52)

271 Pages·2011·1.52 MB·English

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STC89C51(52)RC/RD+ series MCU
STC89LE51(52)RC/RD+ series MCU
Data Sheet
STC MCU Limited
www.STCMCU.com
Update date: 2011-7-25
STC MCU Limited. website：www.STCMCU.com 1
CONTENTS
Chapter 1. Introduction ................................................................6
1.1 Features ..................................................................................................6
1.2 Block diagram ........................................................................................7
1.3 Pin Configurations of STC89C51RC/RD+ series MCU ........................8
1.3.1 Pin Configurations of STC89C51RC/RD+ series HD Version MCU ...................8
1.3.2 Pin Configurations of STC89C51RC/RD+ series 90C Version MCU ..................9
1.4 STC89C51RC/RD+ series Selection Table ..........................................10
1.5 STC89C51RC/RD+ series Minimum Application System ..................11
1.6 STC89C51RC/RD+ series Application Circuit for ISP ........................12
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1.7 Pin Descriptions ................................................t...................................14
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1.8 Package Dimension Drawings ................i..............................................16
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1.9 STC89C51RC/RD+ series MCU n a ming rules ....................................20

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1.10 How to Identify 90C and HD version of STC89xx series MCU ........21
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1.11 Reduce the ElectroMmagnetic Radiation of MCU Clock (EMI) ...........22

— Three Measure s ..................................................................................................22

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1.12 Super Low Power Consumption — STC89xx Series MCU ..............23
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Chapter 2. Power Management and Reset ...............................24
2.1 Power Management Modes ..................................................................24
2.1.1 Idle Mode .............................................................................................................25
2.1.2 Stop / Power Down (PD) Mode ...........................................................................26
2.2 RESET Sources ....................................................................................32
2.2.1 Reset pin ..............................................................................................................32
2.2.2 Software RESET ..................................................................................................32
2.2.3 Power-On Reset (POR) ........................................................................................33
2.2.4 Watch-Dog-Timer ................................................................................................33
2.2.5 Warm Boot and Cold Boot Reset .........................................................................37
Chapter 3. Memory Organization .............................................38
3.1 Program Memory .................................................................................38
3.2 Data Memory ........................................................................................39
3.2.1 On-chip Scratch-Pad RAM ..................................................................................39
3.2.2 Auxiliary RAM ....................................................................................................41
3.2.3 External Expandable 64KB RAM (Off-Chip RAM) ...........................................48
3.3 Special Function Registers ...................................................................49
3.3.1 Special Function Registers Address Map ............................................................49
3.3.2 Special Function Registers Bits Description .......................................................50
3.3.3 Dual Data Pointer Register (DPTR) ....................................................................53
Chapter 4. Configurable I/O Ports of STC89xx series ............55
4.1 I/O Ports Configurations ......................................................................55
4.2 I/O ports Modes ....................................................................................56
4.2.1 Quasi-bidirectional I/O ........................................................................................56
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4.2.2 Open-drain Output (P0 ports are defaut to this mode aftetr reset) ........................57
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4.3 I/O port application notes .....................................................................57
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4.4 Head File/New SFRs Declarations, P4 of STC89C51RC/RD+ series .58

4.5 P4.5/ALE pin of STC89C51RCU/RD+ series 90C version ....................60
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4.6 Typical transistor controMl circuit ...........................................................61

4.7 3V/5V hybrid system ............................................................................61

4.8 I/O drive LEDC application circuit .........................................................62
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4.9 I/O immSediately drive LCD application circuit....................................63
Chapter 5. Instruction System ...................................................64
5.1 Addressing Modes ................................................................................64
5.2 Instruction Set Summary ......................................................................65
5.3 Instruction Definitions ..........................................................................69
Chapter 6. Interrupt System ....................................................106
6.1 Interrupt Structure ..............................................................................108
6.2 Interrupt Register ................................................................................110
6.3 Interrupt Priorities ..............................................................................117
6.4 How Interrupts Are Handled ..............................................................118
6.5 External Interrupts .............................................................................119
6.6 Response Time ..................................................................................123
6.7 Demo Programs about Interrupts (C and Assembly Programs) .........124
6.7.1 External Interrupt 0 (INT0) Demo Programs (C and ASM) .............................124
6.7.2 External Interrupt 1 (INT1) Demo Programs (C and ASM) .............................128
6.7.2 External Interrupt 2 (INT2) Demo Programs (C and ASM) .............................132
6.7.2 External Interrupt 3 (INT3) Demo Programs (C and ASM) .............................137
Chapter 7. Timer/Counter ........................................................142
7.1 Timer/Counter 0/1 ..............................................................................142
7.1.1 Special Function Registers about Timer/Counter 0/1 ........................................143
7.1.2 Timer/Counter 0 Operational Mode (Compatible with traditional 8051 MCU) ........145
7.1.2.1 Mode 0 (13-bit Timer/Counter) .......................................................................................145
7.1.2.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM) ...............................146
7.1.2.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and Assembly Program) ...150
7.1.2.4 Mode 3 (Two 8-bit Timers/Couters) ................................................................................152
7.1.3 Timer/Counter 1 Operational Mode...................................................................153
7.1.3.1 Mode 0 (13-bit Timer/Counter) .......................................................................................153
7.1.3.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASMd) ...............................154
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7.1.3.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C antd ASM) .........................158
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7.2 Application Notes for Timer 0/1 in practice .......................................160
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7.3 Timer/Counter 2 ................................... ..............................................161

7.3.1 Special Function Registers about UTimer/Counter 2 ...........................................161
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7.3.2 Timer / Counter 2 OperaMtional Mode.................................................................163
7.3.2.1 Capture Mode ............ ......................................................................................................163

7.3.2.2 Auto-Reload M o de ..........................................................................................................164
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7.3.2.3 Buad-TRate Generator Mode and Demo Program ( C and ASM) .....................................165
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7.3.2.4 Timer 2 as Programmable Clock Output and Demo Program (C and ASM) ..................172
7.3.2.5 Demo Program of Timer 2 as Timer mode (C and ASM) ...............................................175
Chapter 8. UART with Enhance Function .............................179
8.1 Special Function Registers about UART ............................................179
8.2 UART Operational Modes .................................................................182
8.2.1 Mode 0: 8-Bit Shift Register..............................................................................182
8.2.2 Mode 1: 8-Bit UART with Variable Baud Rate .................................................184
8.2.3 Mode 2: 9-Bit UART with Fixed Baud Rate .....................................................186
8.2.4 Mode3: 9-Bit UART with Variable Baud Rate ..................................................188
8.3 Frame Error Detection ........................................................................190
8.4 Multiprocessor Communications .......................................................190
8.5 Automatic Address Recognition .........................................................191
8.6 Buad Rates and Demo Program .........................................................193
8.7 Demo Program for UART (C and ASM) ...........................................195
Chapter 9. IAP / EEPROM ......................................................201
9.1 IAP / EEPROM Special Function Registers.......................................202
9.2 STC89C51RC/RD+ series Internal EEPROM Allocation Table ........204
9.3 IAP/EEPROM Assembly Language Program Introduction ...............206
9.4 EEPROM Demo Program (C and ASM) ............................................209
Chapter 10. STC89 series programming tools usage .............217
10.1 In-System-Programming (ISP) principle ..........................................217
10.2 STC89C51RC/RD+ series application circuit for ISP .....................218
10.3 PC side application usage .................................................................220
10.4 Compiler / Assembler Programmer and Emulator ...........................222
10.5 Self-Defined ISP download Demo ..................................................222
Appendix A: Assembly Language Programming ...................226
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Appendix B: 8051 C Programming .......................t..................248
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Appendix C: STC89xx series Electrical CLhiaracteristics .......258

Appendix D: Program for indirect a ddressing inner 256B RAM
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Appendix E: Using Seri al port expand I/O interface ............261

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Appendix F: UsTe STC MCU common I/O driving LCD Display
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Appendix G: LED driven by an I/O port and Key Scan ........270
Appendix H: How to reduce the Length of Code using Keil C ...
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Chapter 1. Introduction
STC89C51RC/RD+ series, which is produced by STC MCU Limited, is a 8-bit single-chip microcontroller
with a fully compatible instruction set with industrial-standard 8051 series microcontroller. There is 64K bytes
flash memory embeded for appliaction program, which is shared with In-System-Programming code.In-System-
Programming (ISP) and In-Application-Programming (IAP) support the users to upgrade the program and data
in system. ISP allows the user to download new code without removing the microcontroller from the actual end
product;IAP means that the device can write non-valatile data in Flash memory while the application program
is running. There are 1280 bytes or 512 bytes on-chip RAM embedded that provides requirement from wide
field application. The user can configure the device to run in 12 clocks per machine cycle, and to get the same
performance just as he uses another standard 80C51 device that is provided by other vendor, or 6 clocks per
machine cycle to achieve twice performance. The STC89C51RC/RD+ series retain all features of the standard
80C51. In addition, the STC89xx series have a extra I/O port (P4 ), Timer 2, a 8-sources, 4-priority-level interrupt
structure, on-chip crystal oscillator,and a one-time enabled Watchdog Timer.
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1.1 Features m i
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• Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle

• Operation voltage range: 5.5V~3.3V (STC89C51RC/RD + series) or 2.0V~ 3.6V (STC89LE51RC/RD+ series)
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• Operation frequency range: 0-40MHz @ 6TC, or 0- 80MHz @12T, the actual operation frequency can up to
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48MHz

• On-chip 4K/8K/13K/16K/32K/40 K /48K/56K/61K FLASH program memory with flexible ISP/IAP capability

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• On-chip 1280 byte / 5T12 byte RAM
• Be capable of addSressing up to 64K byte of external RAM
• Be capable of addressing up to 64K bytes external memory
• Dual Data Pointer (DPTR) to speed up data movement
• Three 16-bit timer/counter, Timer 2 is an up/down counter with programmable clcok output on P1.0
• 8 vector-address, 4 level priority interrupt capability
• One enhanced UART with hardware address-recognition, frame-error detection function, and with self baud-
rate generator.
• One 15 bits Watch-Dog-Timer with 8-bit pre-scaler (one-time-enabled)
• integrate MAX810 — specialized reset circuit
• Two power management modes: idle mode and power-down mode
• Low EMI: inhibit ALE emission
• Power down mode can be woken-up by INT0/P3.2 pin, INT1/P3.3 pin, T0/P3.4, T1/P3.5, RXD/P3.0 pin,
INT2/P4.3, INT3/P4.2
• 39 or 35 programmable I/O ports are available
• Four 8-bit bi-directonal ports; extra four-bit additional P4 are available for PLCC-44 and LQFP-44
• Operating temperature: -40 ~ +85oC (industrial) / 0~75oC (commercial)
• package type : LQFP-44, PDIP-40, PLCC-44
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1.2 Block diagram
The CPU kernel of STC89C51RC/RD+ is fully compatible to the standard 8051 microcontroller, maintains all
instruction mnemonics and binary compatibility. STC89C51RC/RD+ series can execute the fastest instructions
per 6 clock cycles or 12 clock cycles(as the same as the standard 80C51). Improvement of individual programs
depends on the actual instructions used.
AUX-RAM RAM ADDR 256 Byte
1024 Byte Register RAM
B Register ACC Dual Data Stack d . FLASH
Poniter Poniter e 64K
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TMP2 TMP1 L i Timer 0/1 ISP/IAP

Timer 2
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Address
C
M UART Generator
ALU

EEP R O M PSW WDT Program
C Counter
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PSEN Port 0,1,2,3,4
Control
ALE Latch
EA Unit
RESET
XTAL1 XTAL2 Port 0,1,2,3,4
Driver
P0, P1,P2,P3,P4
STC89C51RC/RD+ Block Diagram
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1.3 Pin Configurations of STC89C51RC/RD+ series MCU
1.3.1 Pin Configurations of STC89C51RC/RD+ series HD Version MCU
There are not P4.6/P4.5/P4.4 ports in HD version MCU
P0.4P0.5P0.6P0.7EAP4.1ALEPSENP2.7P2.6P2.5 T2ETX2//PP11..01 12 4309 PV0c.c0
P1.2 3 38 P0.1
32109876543 P1.3 4 P 37 P0.2
P0.3 343333222222222 P2.4 P1.4 5 D 36 P0.3
P0.2 35 21 P2.3 P1.5 6 IP 35 P0.4
TI2NETTX23///PPPPPPV111004c......210012c 33334446789012 36LP QIQ/OFFPP P--o44r44ts 21111110987654 XGPPPPX4222TnT....dAA0012LL12 IIRNNTxxTTTDD010/////RPPPPPPP1333133S.......T6043721 78911111e10234 d-40 32 I/O. 3333322243210987 PPPEPPAP00022SAL.....E56776EN
PP11..43 4434 12345678910111132 WRDR//PP33..76 L i WmRTXDR1T///APPP333L...7526i t11115678 Ports 22226543 PPPP2222....5432
P1.5P1.6P1.7RSTRxD/P3.0INT2/P4.3TxD/P3.1INT0/P3.2INT1/P3.3T0/P3.4T1/P3.5 M CP1.4P1.3P1.2UP1.1/T2EXP1.0/T2P4.2/INT3 Vcc P0.0 P0.1 P0.2P0.3 XTAGLn1d 1290 2221 PP22..10
P1.5 7 6 5 4 3 2 1444342414039 P0.4
C P1.6 8 38 P0.5
T P1.7 9 37 P0.6
S RxD/RP3S.T0 1110 PLCC-44 3365 EP0A.7
INT2/P4.3 12 36 I/O Ports 34 P4.1
TxD/P3.1 13 33 ALE
INT0/P3.2 14 32 PSEN
INT1/P3.3 15 31 P2.7
T0/P3.4 16 30 P2.6
T1/P3.5 17181920212223242526272829 P2.5
P3.6P3.7AL2AL1GndP4.0P2.0P2.1P2.2P2.3P2.4
WR/RD/XTXT
About operation voltage/clock frequency: RC/RD+ series MCU are real 6T MCU, which are full compatible
with traditonal 12 clocks per machine cycle
6T core If HD vesion 5V MCU don't double speed, its external clock will divide by 2 in order to lower the
actually frequency
Single speed Operation Double speed Operation
Operation External
Correspond to Clock in Correspond to Clock in IAP/ISP
Voltage Clock
common 8052 actual core common 8052 actual core
5.5V - 4.5V 0 - 44MHz 0 - 44MHz 0 - 20MHz 0 - 80MHz 0 - 40MHz read，program，erase
0 -
5.5V - 3.8V 0 - 33MHz 0 - 33MHz 0 - 66MHz 0 - 33MHz read，program，erase
16.5MHz
5.5V - 3.6V 0 - 24MHz 0 - 24MHz 0 - 12MHz 0 - 48MHz 0 - 24MHz read，program，erase
5.5V - 3.4V 0 - 20MHz 0 - 20MHz 0 - 10MHz 0 - 40MHz 0 - 20MHz read(not program/erase)
3V MCU Operation Voltage range:3.6~2.0V. When operation voltage is 2.3V ~ 1.9V, ISP/IAP do not
be ereased and programmed.
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1.3.2 Pin Configurations of STC89C51RC/RD+ series 90C Version MCU
90C version MCU have P4.6/P4.5/P4.4 but not EA and PSEN pins
P4.5
P0.4P0.5P0.6P0.7P4.6P4.1ALE//P4.4P2.7P2.6P2.5 T2/P1.0 1 40 Vcc
T2EX/P1.1 2 39 P0.0
P0.3 34 333231302928272625242322 P2.4 PP11..23 34 PD 3387 PP00..12
TI2NETTX23///PPPPPPV110004c......100122c 33333445678901 39LP QIQ/OFFPP P--o44r44ts 22111111098765 PPPPPXG42222Tn.....dA00123L1 RTxxDD//RPPPPPP311113S......T045671 5678911 10 IP-40 35 33333336543210 PPPPPPA000004L......734566E/P4.5
PPP111...432 444234 1234567891011111432 XPP33T..A67//LWR2DR IINNTTTT0110////PPPP3333....4532 1111e2345 d I/O Po. 22229876 PPPP2224....7654
P1.5P1.6P1.7RSTP3.0P4.3P3.1P3.2P3.3P3.4P3.5 WRmXDRT//APP33L..726i t111678 rts 222543 PPP222...432
RxD/INT2/TxD/INT0/INT1/T0/T1/ P1.4P1.3CP1.2P1.1/T2EXP1.0/T2UP4.2/INT3VccP0.0 P0.1 P0.2 P0.3 L i XTAGLn1d 1290 2221 PP22..10
M654 3 2 14443424140
PP 11.. 56 78 3398 PP00..45
P1.7 9 37 P0.6
T C RxD/RP3S.T0 1110 PLCC-44 3365 PP40..67
S ITNxTD2/PP34..13 1123 39 I/O Ports 3343 AP4L.1E/P4.5
INT0/P3.2 14 32 P4.4
INT1/P3.3 15 31 P2.7
T0/P3.4 16 30 P2.6
T1/P3.5 17181920212223242526272829 P2.5
P3.6P3.7AL2AL1GndP4.0P2.0P2.1P2.2P2.3P2.4
WR/RD/XTXT
About operation voltage/clock frequency: RC/RD+ series MCU are real 6T MCU, which are full compatible
with traditonal 12 clocks per machine cycle
6T core If 90C vesion 5V MCU don't double speed, its external clock will divide by 2 in order to lower
actually the frequency
Single speed Operation Double speed Operation
Operation External
Correspond to Clock in Correspond to Clock in IAP/ISP
Voltage Clock
common 8052 actual core common 8052 actual core
5.5V - 4.5V 0 - 44MHz 0 - 44MHz 0 - 20MHz 0 - 80MHz 0 - 40MHz read，program，erase
0 -
5.5V - 3.8V 0 - 33MHz 0 - 33MHz 0 - 66MHz 0 - 33MHz read，program，erase
16.5MHz
5.5V - 3.6V 0 - 24MHz 0 - 24MHz 0 - 12MHz 0 - 48MHz 0 - 24MHz read，program，erase
5.5V - 3.4V 0 - 20MHz 0 - 20MHz 0 - 10MHz 0 - 40MHz 0 - 20MHz read(not program/erase)
3V MCU Operation Voltage range:3.6~2.0V. When operation voltage is 2.3V ~ 1.9V, ISP/IAP do not
be ereased and programmed.
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1.4 STC89C51RC/RD+ series Selection Table
E External
12TT/6yTp e8051 Operating MaFxrimequune nCclyock Fal AS TI UA DP EP WInterrupt Interrupt intwehrricuhp ts Pacokfa ge Pa4c4k-apgien of
MCU voltage (Hz) s R M R T R D Sources Priority can wake 40-pin (39 I/O
(V) h M E O T Level up power (35 I/O
T R ports)
(B) (B) R M down ports)
5V 3V (B) mode
STC89C/LE51RC series Selection Table
STC89C51RC 5.5~3.3 0 ~ 80M 4K 512 3 1 2 4K Y 8 4 4 PDIP LQFP/PLCC
STC89C52RC 5.5~3.3 0 ~ 80M 8K 512 3 1 2 4K Y 8 4 4 PDIP LQFP/PLCC
STC89C53RC 5.5~3.3 0 ~ 80M 13K 512 3 1 2 - Y 8 4 .4 PDIP LQFP/PLCC
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STC89LE51RC 3.6~2.0 0 ~ 80M 4K 512 3 1 2 4K Y 8 4 e 4 PDIP LQFP/PLCC
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STC89LE52RC 3.6~2.0 0 ~ 80M 8K 512 3 1 2 4K Y 8m 4 4 PDIP LQFP/PLCC
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STC89LE53RC 3.6~2.0 0 ~ 80M13K 512 3 1 2 - YL 8 4 4 PDIP LQFP/PLCC

STC89C/LE51RD+ serie s S election Table

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STC89C54RD+ 5.5~3.3 0 ~ 80M 16K1280 3 1 2 45KY 8 4 4 PDIP LQFP/PLCC
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STC89C58RD+ 5.5~3.3 0 ~ 80M M32K1280 3 1 2 29KY 8 4 4 PDIP LQFP/PLCC
STC89C516RD+ 5.5~3.3 0 ~ 80M 61K1280 3 1 2 - Y 8 4 4 PDIP LQFP/PLCC

STC89LE54RD+ 3.6~2.0 C 0 ~ 80M16K1280 3 1 2 45KY 8 4 4 PDIP LQFP/PLCC
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STC89LE58RD+ 3.6~2.0 0 ~ 80M32K1280 3 1 2 29KY 8 4 4 PDIP LQFP/PLCC
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STC89LE516RD+ 3.6~2.0 0 ~ 80M61K1280 3 1 2 - Y 8 4 4 PDIP LQFP/PLCC
Besides LQFP-44 and PLCC-44, the packages of STC89C51RC/RD+ series 44-pin MCU also have PQFP, in
which the PLCC-44 and PQFP-44 do not be recommended for users. So we recommend to select the LQFP-44
package as possible.
The reasons to select STC MCU : lower cost and boost performance. All the original programs can be used
directly without any change of hardware. Users can download their bin or hex code to STC MCU by the Writer /
Programmer tool — STC-ISP.exe.
Internal Flash can be rewritable repeately more than 100 thousands times
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