Speed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs

154 Pages·2014·25.28 MB·English

by  Beanato, Giulia

Speed/Power/Area Trade-offs for High Speed Inter Layer
Data Transmission in 3D Stacked ICs
THÈSE NO 6278 (2014)
PRÉSENTÉE LE 26 AOÛT 2014
À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEUR
LABORATOIRE DE SYSTÈMES MICROÉLECTRONIQUES
PROGRAMME DOCTORAL EN MICROSYSTÈMES ET MICROÉLECTRONIQUE
ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE
POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCES
PAR
Giulia BEANATO
acceptée sur proposition du jury:
Dr G. Boero, président du jury
Prof. Y. Leblebici, Prof. G. De Micheli, directeurs de thèse
Prof. A. P. Burg, rapporteur
Dr F. Clermidy, rapporteur
Prof. A. K. Coskun, rapporteuse
Suisse
2014

Consideratelavostrasemenza:
fattinonfosteavivercomebruti,
maperseguirvirtuteecanoscenza.
—DanteAlighieri
Tothememoryofmygrandmas...

Acknowledgements
Thisdissertationisthefinalsnapshotoffourandahalfyearsofdays,nightsandweekends
diggingintosomeofthemanychallengessomeonefacesinordertostackmultiplesilicon
layers.Noneofthisworkwouldhavebeenaccomplishedifitwasn’tforProf.YusufLeblebici
andProf. GiovanniDeMicheli,whogavemetheopportunitytopursuethisresearchand
guidedmethroughoutit. Researchisanendlesstaskthatrapidlybecomesanaddiction. I
havetothankthememberofthethesiscommitteeProf.Burg,Prof.Coskun,Dr.Clermidyand
Prof.Boero,forevaluatingmyworkputtinganendtomyPhDdependence.
DuringtheseyearsIhadthechancetosharethelabwithbothamusingandtalentedpeople.
AmongthemIhavetoparticularlyacknowledgeseveralpersonsthatmarkedmylife. My
officemateAlewhosupportedmebothtechnicallyandasafriend,weneverstoppedarguing
andfighting,itwasfunandIlearnedalot. Hossein,abrilliantofficematefor3yearsand
aremarkableperson. KiarashandMahsawhoprovidedforthe"tucoftheday"andgreat
supportwhileIwasstrugglingwithendlessproblems,IreallyhopeI’vehelpedthematleast
halfasmuchasthey’vehelpedme.DavidewholistenedtomewhenIreallyneeded.Yuksel,
Michael,Paolo,Igorandallthepeoplethatsharedtheirknowledgeandexperiencewithme.I
amextremelygratefultoAlainforhiseverlastingpatienceregardingallthetimesIknockedon
hisdoorwithsomelinux-relatedissue.IwouldnotdareimagininghowcouldIhaveendured
withouttheinvaluablesupportofMarieandMelinda.
Then,IshouldadmitIoweabigdebtofgratitudetomyPhD,forgivingmetheopportunity
torunintoamazingpeoplelikeSara,Francesco,Alessia,Romain,Erifili,Marco(s),Mauro,
Andrea(s),Luca,Alessandro(s),Stefano,... andallthefriendsIwassoluckytomeetbutI
cannotmentiononebyonewithoutoccupyingtoomanypages.
ThelastyearofaPhDissupposedtobethemoststressful,butthankstomysisterwhohad
thecouragetocomelivewithmeandthetheatregroupsIjoinedIwillrememberitasan
amazingyear.IhavetothanktheImproPasforalltheamusementandlaughterwehadwhile
bringingnewpeopleandsituationsintobeing.AtthesametimeI’malsoextremelygratefulto
theCatalystandallthe"enemiesofthepeople"whoacceptedmeaspartofthegroup.Ihada
wonderfultimeandalotoffunrehearsingalmosteverydaywithallofyou,wehadagreatrun.
IdooweareallyspecialthanktoPaolo,EnricoeWolty,althoughthekilometresareseparating
us,they’vealwaysbeenthereformeandIknowIcanalwayscountonthemwhenIneed.
Finally,thedeepestthankshouldgotoGraziana,GigiandElena.Familyisthemostimportant
thinginlife,anythingIachievedandwillachieveisworthitjustbecauseIcanshareitwith
them.
v
Acknowledgements
Grazie!
Lausanne,19June2014 G.B.
vi
Abstract
TechnologyscalingisnowstrugglingtomeettheexpectationsdictatedbyMoore’sLawdueto
complexityandcost.Inparticular,interconnectshavebecomeamajorperformancebottle-
neckforplanarchipmulti-processorsandarerapidlydominatingdieareaandpowerdissipa-
tion.Theselimitingfactorsneedtobeaddressedatthearchitecturallevel.Apromisingoption
exploredinthelastfewyearsareThreeDimensional(3D)architecturesexploitingThrough
SiliconVia(TSV).Infact,TSVinterconnectshavethepotentialtoreducetheinterconnectwire
lengthand,atthesametime,offerhighverticalconnectiondensity.
Inthelastdecadeseveralgroupsinbothacademiaandindustryhavedevelopedtheirown
TSVtechnologyexploitingdifferentdesigns,fabricationtechniquesandmaterials.Giventhe
diversityoftheparameterscharacterizingTSVtechnology,thechoiceofthemostappropriate
3Dinterconnectforaspecificdesignisofutmostimportance.Nevertheless,thesiliconarea
overheadduetotheTSVinsertionandthenon-negligibleTSVcapacitancemighthinderthe
performanceimprovementsofferedby3D-ICs.Hence,theICdesignersarenowrequiredto
findcircuitdesigntechniquesthatfullyexploitthepotentialoftheavailable3Dinterconnects.
Thisdissertationdiscussescircuitdesignsolutionsforcross-chipcommunicationthrough
state-of-the-artTSVchannels.DifferentTSVchannelsandinterconnecttopologieshavebeen
exploredwiththeaimofachievingthearea,powerandperformancerequirementsof3D-
stackedsystems.Morespecifically,thecontributionofthisthesisconsistsofproposingdesign
solutionstoleveragethehighbandwidthandlow-delayconnectionprovidedbyTSVlinks
minimizingthecostintermsofsiliconareaandcapacitance.
A silicon-proven analytical model of the TSV channel is presented, which provides good
correlation between simulations and chip measurements. The model is then extensively
utilizedtoemulatethe3DI/Olinkswhiledesigningtheinterconnectcircuits.
Thefollowingpartsofthethesisaimstodemonstratetheefficiencyofdifferent3Dintercon-
nectiontopologiesincompletesystems.Aconfigurablenetworkarchitectureexploitingafully
parallelTSVbusisproposed.Thegoalistocreateasystemcomposedofaclusterofprocess-
ingelements,placedonalogiclayer,andmultiplelayersofSRAMmodulesconstitutinga
singlesharedL1memory. Theperformanceofashared-L1memorycriticallydependson
thearchitectureoftheinterconnectbetweenprocessorsandmemorybanks. Therequired
low-latencycommunicationisachievedbya3Dlogarithmicnetworkstructure. Thisarchi-
tectureshowssignificantimprovementsinbothareaandlatencycomparedtotheplanar2D
implementation.
Nevertheless,aparallelTSVbusisstillextremelyareaconsuming.Inordertobalanceinter-
vii
Abstract
layerbandwidthofferedbyTSVsandtheirsiliconareaoccupation,ahighdata-rate3Dserial
linkisproposed.Thehigh-speedserial3Dlinkoptimizesboththeinter-layercommunication
speedandtheinterconnectareaoccupation,stillguaranteeinglow-powercommunication.
Theproposedserializer-deserializer(SERDES)circuitshavebeenexploredacrossavarietyof
state-of-the-artTSVtechnologies.
Amodular3Dstackedmulti-processorplatform,3D-MMC,featuringthe3Dserialconnection
macrohasbeendesignedtodemonstratethepotentialoftheproposedinterconnecttopology.
Theanalysisofthesystems’wiringcharacteristicsdemonstratesthatthereductioninthe
numberofTSVsobtainedwiththeadoptionoftheserialverticalconnectionimprovethe
routingcongestionofthe3Dsystem.
In the final part of this dissertation, a test vehicle based on the 3D-MMC architecture is
presented.Aprototypeofthe3Dmulti-processorsystemhasbeendesigned,fabricatedand
tested. Thefinal3DsystemhasbeenobtainedbystackingKnownGoodDies(KGD)using
anin-housevia-lastTSVprocess. Theexperimentalresultsobtainedfromsimulationsand
measurementsonthefabricatedsamplesdemonstratethatthesystemexhibitsmultipleGbps
verticaldatabandwidthwhilelimitingthenumberofTSVs.
Finally,thethesisisconcludedwithasummaryofthecontributionsandadiscussiononthe
futurework.
Keywords:3DICs,ThroughSiliconViasTSVs,ChipMulti-ProcessorsCMPs,highspeedserial
links.
viii
Sommario
L’aumentodellacomplessitàedelcostolegatoallariduzionedelledimensionidellatecnologia
CMOSstannorendendosemprepiúdifficilerispettareleaspettativedettatedallaleggedi
Moore.Inparticolare,leinterconnessionisonodiventateunadellemaggioricauselimitanti
perleprestazionideimultiprocessoriplanariestannorapidamentedominandosial’area
cheilconsumodipotenzadeichip.Questifattorilimitantidevonoessereaffrontatialivello
architetturale. Una promettente opzione esplorata negli ultimi anni sono le architetture
tridimensionalicheutilizzanoleinterconnessioniattraversoilsilicio,TSVs. Infatti,leTSV
hanno la caratteristica di ridurre la lunghezza delle interconnessioni offrendo allo stesso
tempoun’altadensitàdiconnessioneverticale.
Nell’ultimo decennio diversi gruppi sia in accademia che in industria hanno sviluppato
lapropriatecnologiadifabbricazionedelleTSVutilizzandodifferentidesign, technichee
materiali.DataladiversitàdeiparametrichecaratterizzanoletecnologieTSV,lasceltadella
tecnologiapiúadattaperunparticolaredesignédiprimariaimportanza. Nonostanteció,
l’aumento dell’area dovuta all’instanziamento delle TSV e la loro capacità parassita non
trascurabilepotrebberooffuscareibeneficioffertidallatecnologia3D.Diconseguenza,nuove
tecniche di design devono essere esplorate per sfruttare al massimo le potenzialità della
tecnologia3D.Questatesiproponesoluzionicircuitaliperlacomunicazionetradiversichip
attraverso le TSV disponibili oggi. Varie TSV e topologie di interconnessione sono state
esplorateconloscopodiraggiungereleaspettativesulleprestazionipromessedallatecnologia
3D.Inparticolare,ilcontributodiquestatesiconsistenelproporresoluzioniperottimizzareil
compromessotral’altabandaelavelocitàdelleTSVriducendoalminimoilcostointermini
diutilizzodiareaecapacitàparassita.
ComeprimacosavienepresentatounmodelloanaliticodelleTSVvalidatodamisuresusilicio,
garantendoquindiunabuonacorrelazionetrasimulazioniemisure.Ilmodellovienequindi
ampiamenteutilizzatoperemulareillink3Dduranteildesigndeicircuitidiinterconnessione.
La parte seguente dellatesi hacome scopo dimostrare l’efficienzadi diverse topologie di
interconnessione inserite in sistemi completi. Viene proposta un’architettura di network
combinatoriacheutilizzaunbusparallelodiTSV.Loscopoèdiinterconnettereunsistema
composto da un gruppo di processori localizzati su un layer di logica, ad una memoria
condivisadiprimolivellocompostadavarilayeroccupatidablocchidiSRAM.L’architettura
dell’interconnessionetraprocessoriememoriaèunfattorecriticoperleprestazionidiuna
memoriadilivello1condivisa.Lacomunicazioneabassalatenzavieneottenutatramiteuna
strutturadinetworklogaritmicain3D.Questaarchitetturamostraunincrementosignificativo
ix
Abstract
siainterminidiareachelatenzasecomparataall’implementazioneplanarein2D.
CiónonostanteunbusparallelodiTSVoccupaunaporzionesignificantediarea.Un3Dlink
serialeadaltavelocitàvienequindipropostoperbilanciarelabandwidthoffertadalleTSV
elaloroarea. Il3Dlinkserialeadaltavelocitàottimizzasialacomunicazionetralayerche
l’occupazionediarea,garantendoallostessotempounbassoconsumoinpotenza.Icircuiti
diserializzazione-deserializzazionesonostatiesploratiperdiversetecnologiediTSV.
Unmulti-processoremodularetridimensionale,3D-MMC,cheutilizzaunaconnessioneinter-
layerserialeèstatoprogettatoperdimostrarelepotenzialitàdellatopologiaproposta.L’analisi
delle interconnessioni del sistema dimostra che la riduzione del numero di TSV ottenuta
attraversolaserializzazioneriducelacongestionedelrouting.
Nellapartefinaledellatesivienepresentatounprototipochesibasasull’architettura3D-MMC.
Ilprototipodelmulti-processore3Dèstatoprogettato,fabbricatoetestato.Ilsistema3Dfinale
èstatoottenutomettendounosopral’altroichiptestatifunzionanti,interconnettendolicon
unprocessodifabbricazionedelleTSVsviluppatoin-house.Irisultatisperimentaliottenuti
dallesimulazioniedallemisuresuichipfabbricatidimostranocheilsistemapuóarrivarea
funzionareadiversiGbpsdibandwidthverticalelimitandoilnumerodiTSV.
Infine,latesisiconcludeconunsommariodeicontributiscientificiedunadiscussionesul
lavorodasviluppareinfuturo.
Parolechiave:3DICs,ThroughSiliconViasTSVs,ChipMulti-ProcessorsCMPs,highspeed
seriallinks.
x