signal preconditioning using feedforward equalizers in adc-based data links a dissertation ...

158 Pages·2016·3.11 MB·English

SIGNAL PRECONDITIONING USING FEEDFORWARD
EQUALIZERS IN ADC-BASED DATA LINKS
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL
ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Ryan Boesch
May 2016
© 2016 by Ryan Boesch. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons Attribution-

Noncommercial 3.0 United States License.
http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/dk653rc7126

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I certify that I have read this dissertation and that, in my opinion, it is fully adequate
in scope and quality as a dissertation for the degree of Doctor of Philosophy.
Boris Murmann, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequate
in scope and quality as a dissertation for the degree of Doctor of Philosophy.
Mark Horowitz
I certify that I have read this dissertation and that, in my opinion, it is fully adequate
in scope and quality as a dissertation for the degree of Doctor of Philosophy.
Madihally Narasimha
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost for Graduate Education
This signature page was generated electronically upon submission of this dissertation in
electronic format. An original signed hard copy of the signature page is on file in
University Archives.
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Abstract
As the data rates for high-speed wireline transceivers continue to increase, inter-
symbol interference (ISI) due to channel loss is becoming more pronounced and mul-
tiple techniques have been suggested to address this issue. One technique that has
recently been gaining popularity is the ADC-based receiver. In ADC-based receivers,
a digital feedforward equalizer (FFE) is used in conjunction with a decision feedback
equalizer (DFE) to equalize the channel and recover the data. However, in order to
recover the data with a high fidelity, a power-hungry ADC is needed to digitize the
signal. Recent work has shown that an analog receive-side FFE (RX-FFE) prior to
the ADC can reduce the required ADC resolution while achieving the same BER.
In order to obtain a net improvement for the system, the RX-FFE must be imple-
mented with low power consumption, low noise, and small chip area. In this thesis, an
RX-FFEisdemonstratedthatmeetstheserequirementsandoutperformsstate-of-the-
art designs. The RX-FFE is constructed entirely with low-noise and power-efficient
analog-inverter transconductors and capacitors, avoiding the use of area-intensive in-
ductors. Thedelayelementisimplementedasasingle-pathPad´e-inspireddelayshown
to be equivalent to the first-order Pad´e delay in terms of RX-FFE performance. The
proof-of-concept RX-FFE is demonstrated to reduce the signal dynamic range by 2×
resulting in a 1bit ADC resolution relaxation. The total power consumed is less than
26mW with less than 0.62mV output noise for all coefficient values and an area
RMS
of only 0.003mm2 in 40nm CMOS.
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Acknowledgments
I have been fortunate to interact with so many wonderful people during the course
of my Ph.D. I want to take this opportunity to thank those who played a big role in
the completion of this work.
Firstly, I must thank my advisor Professor Boris Murmann. My success in this
program can largely be attributed to his guidance and support. He has been a better
advisor than I could have dreamed of finding when I first started on this journey.
I also thank Professor Mark Horowitz and Dr. Madihally Narasimha for being
on my reading committee. I thank Professor Amin Arbabian for being on my orals
committee and Professor Jon Fan for chairing the orals committee.
I thank the Broadcom Foundation and Stanford’s initiative for Rethinking Analog
Design for the funding that they provided. I thank the TSMC University Shuttle
Program for the integrated circuit fabrication they provided.
Thanks to Tom Kwan from Broadcom for arranging presentations and providing
early feedback on my work. Thanks to Hiroshi Takatori, John Duan, and Albert
Vareljian from Futurewei for help with chip debugging and for access to test equip-
ment. Thanks to Frankie Liu and Vincent Lee from Oracle for access and support
with test equipment.
I thank Ann Guerra for all the administrative help she provided throughout my
degree. She has always gone above and beyond for me and all of the students in the
Murmann group. We are lucky to have her. In addition, I thank Joe Little for his
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IT support. The speed with which he replies to emails and resolves server issues is
paramount and I am greatly appreciative of the help I have received from him over
the years.
I would also like to thank everyone in the Murmann group, past and present. In
particular, thanks to Jonathon Spaulding, Doug Adams, and Martin Kraemer for the
trips aboard and for good times back home.
Last but not least, I thank my family whose love and support mean everything
to me. To my sister — you have been a role model of mine my entire life. Thanks
for setting the bar so high. To my brother — you continue to impress me each day.
I am proud of what you have accomplished and excited to see what you will achieve
next. To my mother - I am lucky to have enjoyed your unwavering support and
unconditional love. I certainly would not have made it here without you. To my wife
— I do not think I could have finished this degree without you. Meeting you is the
best thing to ever happened to me.
Finally, I dedicate this thesis to the memory of my father. All of the best parts
of who I am today can be traced back to you.
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Contents
Abstract v
Acknowledgments vi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Background 8
2.1 Channel characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Transmission line model . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Linear system model . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 Pulse response . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.4 Typical channels . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Receive feedforward equalizer (RX-FFE) . . . . . . . . . . . . . . . . 14
2.2.1 FFE operation . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Metrics of FFE performance . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 Peak-to-main ratio (PMR) . . . . . . . . . . . . . . . . . . . . 17
2.3.2 Eye opening equivalence . . . . . . . . . . . . . . . . . . . . . 20
3 Analog delays for FFEs 23
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3.1 Delay approximations . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.1 Ideal delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.2 Lumped delay line . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3 Bessel delays . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.4 Pad´e delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Equivalence of first-order delays . . . . . . . . . . . . . . . . . . . . . 30
3.2.1 Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 Coefficient spread . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.3 Example transformation . . . . . . . . . . . . . . . . . . . . . 32
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Analog FFEs in high-speed links 37
4.1 FFE design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 Simulation methodology . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3 Delay type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4 Delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4.1 Mathematical analysis . . . . . . . . . . . . . . . . . . . . . . 41
4.4.2 Channel characteristic dependence . . . . . . . . . . . . . . . 43
4.4.3 First-order delays . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5 Number of taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6 Parasitic pole frequency . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.7 Coefficient resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.8 Main cursor attenuation . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 Inverter-based FFE 52
5.1 Analog-inverter transconductor . . . . . . . . . . . . . . . . . . . . . 52
5.2 Unity-gain stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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5.2.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.2 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2.4 Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2.5 Supply rejection . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2.6 Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1 Single-path Pad´e-inspired delay . . . . . . . . . . . . . . . . . 61
5.3.2 Comparison with two-path Pad´e delay . . . . . . . . . . . . . 64
5.4 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.5 Summing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.6 Full FFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.6.1 FFE noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.6.2 FFE mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6 FFE design 71
6.1 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.2 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3 Summing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.4 PRBS generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5 Output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7 Measurement results 77
7.1 Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.1.1 On-chip channel . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.1.2 Off-chip channel . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2 Test debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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