Serial Parallel Addition Multiplier

41 Pages·2009·1.58 MB·English

by  Ajit Prasad (4634888)

SERIAL – PARALLEL ADDITION MULTIPLIER

AJIT PRASAD
ID: 4634888

Digital Design & Synthesis
COEN 6501
Department of
Electrical & Computer Engineering
Concordia University
December 2005
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TABLE OF CONTENTS

INTRODUCTION 5
.1 VHDL Design Process 5
.2 Report Breakdown 5

MULTIPLIER DESIGN 6
.1 Multiplier Operation 6
.2 Full Adder 7
.3 D Flip-Flop 9
.4 Parallel Load Shift Register 10
.5 Parallel Load Parallel Output Register 11
.6 Serial-Input Parallel Output Register 11
.7 Multiplier Controller 12
.8 Integrated Multiplier 14

DESIGN ENHANCEMENTS 16
.1 32 X 32-Bit Expansion 16
.2 Pipelined Design 16
.3 Synthesized Design 16

CONCLUSION 17

5.0 REFERENCES 18

APPENDIX A: VHDL SOURCE 19
APPENDIX B: SYNTHESIS 29
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LIST OF FIGURES

Figure 1.1 VHDL Design Process…………………………………………………………………………. 5
Figure 2.1 Serial-Parallel Multiplier……………………………………………………………………….. 6
Figure 2.2 Multiplier Block Diagram………………………………………………………………………. 7
Figure 2.3 Full Adder K-Map………………………………………………………………………………. 8
Figure 2.4 Full Adder Schematic………………………………………………………………………….. 8
Figure 2.5 Full Adder Simulation………………………………………………………………………….. 8
Figure 2.6 Positive Edge Triggered D Flip-Flop With Asynchronous Reset…………………………. 9
Figure 2.7 D Flip-Flop Simulation…………………………………………………………………………. 10
Figure 2.8 Parallel Load Shift Register…………………………………………………………………… 10
Figure 2.9 Parallel Load Shift Register Simulation……………………………………………………… 10
Figure 2.10 Parallel Load Parallel Output Register………………………………………………………. 11
Figure 2.11 Parallel Load Parallel Output Register Simulation………………………………………….. 11
Figure 2.12 Serial-Input Parallel Output Register………………………………………………………….11
Figure 2.13 Serial-Input Parallel Output Register Simulation……………………………………………. 12
Figure 2.14 Multiplier Controller State Machine…………………………………………………………... 12
Figure 2.15 Multiplier Controller Schematic……………………………………………………………….. 13
Figure 2.16 Multiplier Controller Simulation……………………………………………………………….. 14
Figure 2.17 8 by 8-Bit Serial-Parallel Multiplier Simulation………………………………………………. 14
Figure 3.1 32 By 32-Bit Multiplier Simulation…………………………………………………………….. 16
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LIST OF TABLES

Table 2.1 Full Adder Truth Table…………………………………………………………………………. 7
Table 2.2 D Flip-Flop Characteristic Table……………………………………………………………… 9
Table 2.3 Multiplier Controller State Table………………………………………………………………. 13
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INTRODUCTION

The objective is to design an 8 by 8-bit serial-parallel multiplier using structural VHDL. The multiplier
receives two operands A and B, and calculates the result C. The multiplier will be further expanded to
32 by 32-bit multiplication, pipelined, and synthesized.

1.1 VHDL Design Process

The design procedure that will be followed is shown in figure 1.1 below. The target device is the Xilinx
xc3s200 FPGA from the Spartan family of devices. This document will illustrate the design process
from design entry to design implementation of the multiplier.

Figure 1.1 VHDL Design Process [1].

1.2 Document Breakdown

This document breaks the multiplier down into major blocks and designs each block independently
before finally assembling the complete multiplier. Each block is coded in purely structural VHDL
therefore it is necessary to conceive the schematic of each block in advance. To ensure that each block
works as intended it will be simulated and important timing parameters will be extracted.
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2.0 MULTIPLIER DESIGN

The multiplier uses the serial-parallel method of addition to calculate the result of multiplying two 8-bit
numbers as shown in figure 2.1 below. The multiplier receives the two operands A and B and outputs
the result C. Operands A and B are loaded in parallel into 8-bit registers and the result C is shifted into
a 16-bit register. Multiplication begins on the assertion of a START signal and once the calculation is
complete a STOP signal is asserted.

Figure 2.1 Serial-Parallel Multiplier.

2.1 Multiplier Operation

The serial-parallel multiplier is based on the addition of bits in the corresponding column of the
multiplication process as shown below. Each column is added in one clock cycle generating the
corresponding bit. The resulting bit is then shifted into output register. Therefore the entire multiplication
process for the 8 by 8-bit multiplier requires 16 clock cycles to complete the calculation.

a1a0
x b1b0
------------------------------------
a1b0 a0b0
a1b1 a0b1
------------------------------------
a1b1 (a1b0 + a0b1) a0b0

The block diagram for the multiplier is shown in figure 2.2 below. The first operand, A, is loaded in
parallel and the most significant bit is shifted out during each clock cycle. Operand B is also loaded in
parallel and its value is stored in the register for the entire multiplication process. The result C is
generated by shifting the added bits of each column one by one into the resultant register. Therefore
register RA is a parallel load shift register, RB is a parallel load parallel output register, and RC is a
serial input parallel output register.
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Figure 2.2 Multiplier Block Diagram.

In addition to the three mentioned registers, the multiplier also requires 7 one-bit registers to store
intermediate values such as the carries generated from each addition, and the bits shifted out from
register RA.

Each component to the multiplier is designed and simulated in the following sections.

* It is important to note that all clocked circuits below use an asynchronous active low reset denoted as
Resetn, and a clock period of 20 ns.

* For the complete VHDL code for the multiplier and its components refer to Appendix A.

2.2 Full Adder

Part of the partial product sum ripple adder block, the full adder is a combinational circuit that calculates
the sum of three bits. The resulting sum is output along with the carry. The truth table and K-maps for
the full adder is shown below in table 2.1 and figure 2.3.

Table 2.1 Full Adder Truth Table.
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Figure 2.3 Full Adder K-Map [2].

Therefore the simplified expressions for the full adder are

S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz

Grouping the above expressions appropriately, the full adder can be constructed using two half adders
and an OR gate

S = z  (x  y)
C = z(xy’ + x’y) + xy

The implementation of the full adder is therefore

Figure 2.4 Full Adder Schematic [2].

The result of simulating the circuit is shown in figure 2.5 below.

Figure 2.5 Full Adder Simulation.

Although it is not obvious from the schematic, the simulation reveals that the maximum delay of the
circuit is the time it takes for the sum output to be generated (which indicates that the XOR gate has the
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largest delay compared to the AND or OR gates). In this case the delay of the full adder circuit is
approximately 8.196 ns.

2.3 Edge Triggered D Flip-Flop

The positive edge triggered D flip-flop with asynchronous reset is used throughout as the main register
type to store various bit values for the multiplier. The characteristic table for the D flip-flop is shown in
table 2.2 below. For this type of register the next output is simply the present input.

Table 2.2 D Flip-Flop Characteristic Table.
D Q(t+1)
0 0 Reset
1 1 Set

An efficient implementation of a D flip-flop uses three SR latches as shown in figure 2.6. Two latches
respond to the CLK and Data inputs. The third SR latch generates the outputs Q and its complement Q’
[2].

Figure 2.6 Positive Edge Triggered D Flip-Flop With Asynchronous Reset [2].

The result of simulating the circuit is shown in figure 2.7.
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Figure 2.7 D Flip-Flop Simulation.

The delay from the clock input to the output is approximately 11.678 ns.

2.4 Parallel Load Shift Register

The 8-bit parallel load shift register is composed of multiplexers and D flip-flops, refer to figure 2.8. The
multiplexers select whether to load the data or to simply pass the previous register value. If neither the
load or shift enable inputs are high the registers keep their current values. If both inputs are high then
the load input takes precedence. Otherwise the circuit either loads or shifts at each clock cycle with
respect to the input that is high. If the circuit is shifting then a 0 is introduced at the leftmost bit.

Figure 2.8 Parallel Load Shift Register.

The result of simulating the circuit is shown in figure 2.9 below.

Figure 2.9 Parallel Load Shift Register Simulation.

Since in either the loading or shifting case data must travel from the input of the LSB multiplexer to the
output shift bit the delay is equal at approximately 14.891 ns. Knowing from the previous simulation that
the D flip-flop has a delay of 11.678 ns we can induce that the multiplexer has a delay of approximately
3.213 ns.