Sequential logic and Verilog HDL fundamentals

858 Pages·2016·15.397 MB·English

by  Cavanagh, Joseph J. F

Computer Science & Engineering Cavanagh
Sequential Logic and Verilog
HDL Fundamentals
“… thorough coverage of counter design. … [a] good introductory text for Verilog.”
—Parag K. Lala, Texas A&M University-Texarkana, USA
S
Sequential Logic and Verilog HDL Fundamentals discusses the analysis
and synthesis of synchronous and asynchronous sequential machines. These e
machines are implemented using Verilog Hardware Description Language
q
(HDL), in accordance with the Institute of Electrical and Electronics Engineers
u
(IEEE) Standard: 1364-1995. H
e
The book concentrates on sequential logic design with a focus on the design D
n
of various Verilog HDL projects. Emphasis is placed on structured and rigor-
L
ous design principles that can be applied to practical applications. Each step t
of the analysis and synthesis procedures is clearly delineated. Each method i
Fa
that is presented is expounded in sufficient detail with accompanying exam-
ul
ples. Many analysis and synthesis examples use mixed-logic symbols incor-

porating both positive- and negative-input logic gates for NAND (not AND) nL
and NOR (not OR) logic, while other examples utilize only positive-input logic do
gates. The use of mixed logic parallels the use of these symbols in the
ag
industry.
mi
The book is intended to be a tutorial, and as such, is comprehensive and c
self-contained. All designs are carried through to completion—nothing is left e
unfinished or partially designed. Each chapter contains numerous problems of a
n
n
varying complexity to be designed by the reader using Verilog HDL design
t d Sequential Logic
techniques. The Verilog HDL designs include the design module, the test
aV
bench module that tests the design for correct functionality, the outputs
obtained from the test bench, and the waveforms obtained from the le
s
test bench. r

i
Sequential Logic and Verilog HDL Fundamentals presents Verilog HDL l Verilog HDL
with numerous design examples to help the reader thoroughly understand this o
and
popular hardware description language. The book is designed for practicing g
electrical engineers, computer engineers, and computer scientists; for gradu-
ate students in electrical engineering, computer engineering, and computer
science; and for senior-level undergraduate students. Fundamentals

K26575
ISBN: 978-1-4987-3822-4
90000 Joseph Cavanagh
9 781498 738224
Sequential Logic
Verilog HDL
and
Fundamentals
TThhiiss ppaaggee iinntteennttiioonnaallllyy lleefftt bbllaannkk
Sequential Logic
Verilog HDL
and
Fundamentals

Joseph Cavanagh
Boca Raton London New York
CRC Press is an imprint of the
Taylor & Francis Group, an informa business
CRC Press
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© 2016 by Taylor & Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group, an Informa business
No claim to original U.S. Government works
Version Date: 20150825
International Standard Book Number-13: 978-1-4987-3823-1 (eBook - PDF)
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Visit the Taylor & Francis Web site at
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In memory of Ivan Pesic and for his wife Kathy and son Illya
Founders and owners of Silvaco, Inc.
for generously providing the SILOS Simulation Environment software
for all of my books that use Verilog HDL and for their continued support
TThhiiss ppaaggee iinntteennttiioonnaallllyy lleefftt bbllaannkk
CONTENTS
Preface ............................................................................................. xi
Chapter 1 Introduction to Verilog HDL .......................... 1
1.1 Built-In Primitives .............................................................. 2
1.2 User-Defined Primitives .................................................... 18
1.2.1 Defining a User-Defined Primitive .................... 18
1.2.2 Combinational User-Defined Primitives ........... 19
1.3 Dataflow Modeling ............................................................ 35
1.3.1 Continuous Assignment ..................................... 35
1.3.2 Reduction Operators .......................................... 41
1.3.3 Conditional Operator ......................................... 45
1.3.4 Relational Operators .......................................... 48
1.3.5 Logical Operators .............................................. 50
1.3.6 Bitwise Operators .............................................. 53
1.3.7 Shift Operators ................................................... 59
1.4 Behavioral Modeling .......................................................... 63
1.4.1 Initial Statement ................................................. 64
1.4.2 Always Statement .............................................. 66
1.4.3 Intrastatement Delay .......................................... 70
1.4.4 Interstatement Delay .......................................... 73
1.4.5 Blocking Assignments ....................................... 75
1.4.6 Nonblocking Assignments ................................. 78
1.4.7 Conditional Statements ...................................... 81
1.4.8 Case Statement ................................................... 85
1.4.9 Loop Statements ............................................... 89
1.5 Structural Modeling ........................................................... 91
1.5.1 Module Instantiation .......................................... 91
1.5.2 Ports ................................................................... 92
1.5.3 Design Examples ............................................... 93
1.6 Problems ............................................................................ 113
Chapter 2 Synthesis of Synchronous Sequential
Machines 1 Using Verilog HDL .................... 121
2.1 Synchronous Registers ....................................................... 122
2.1.1 Parallel-In, Serial-Out Registers ........................ 122
2.1.2 Serial-In, Parallel-Out Registers ........................ 131
2.1.3 Serial-In, Serial-Out Registers ........................... 143
2.1.4 Combinational Shifter ........................................ 151
viii Contents
2.2 Synchronous Counters ....................................................... 173
2.2.1 Modulo-8 Counter ............................................. 174
2.2.2 Modulo-10 Counter ........................................... 186
2.2.3 Johnson Counter ................................................ 206
2.2.4 Binary-to-Gray Code Converter ........................ 219
2.3 Moore Machines ................................................................ 233
2.3.1 Design Using Behavioral Modeling ................... 235
2.3.2 Design Using Structural Modeling with D Flip-
Flops, AND Gates, and an OR Gate ................... 239
2.3.3 Design Using Structural Modeling with D Flip-
Flops, NOR Gates, and an OR Gate ................... 244
2.3.4 Design Using Structural Modeling with
JK Flip-Flops, AND Gates, and an OR Gate ..... 249
2.4 Mealy Machines ................................................................. 254
2.4.1 Design Using Behavioral Modeling ................... 255
2.4.2 Design Using Structural Modeling with D Flip-
Flops .................................................................. 259
2.4.3 Design Using Structural Modeling with JK
Flip-Flops ........................................................... 265
2.5 Moore–Mealy Equivalence ................................................ 270
2.6 Output Glitches .................................................................. 317
2.6.1 Glitch Elimination Using State Code
Assignment ........................................................ 317
2.6.2 Glitch Elimination Using Complemented Clock 322
2.6.3 Glitch Elimination Using Delayed Clock .......... 334
2.7 Problems ............................................................................ 340
Chapter 3 Synthesis of Synchronous Sequential
Machines 2 Using Verilog HDL .................... 347
3.1 Multiplexers for  Next-State Logic .................................. 348
3.1.1 Linear-Select Multiplexers ................................ 349
3.1.2 Nonlinear-Select Multiplexers ........................... 376
3.2 Decoders for  Output Logic .............................................. 392
3.3 Programmable Logic Devices ............................................ 421
3.3.1 Programmable Read-Only Memory ................... 422
3.3.2 Programmable Array Logic ............................... 426
3.3.3 Programmable Logic Array ............................... 445
3.4 Iterative Networks .............................................................. 460
3.5 Error Detection in Synchronous Sequential Machines ....... 473
3.5.1 Overview of Error Detection and Correction ..... 473
3.5.2 Examples of Error Detection in Synchronous
Sequential Machines .......................................... 478
3.6 Problems ............................................................................ 491
Contents ix
Chapter 4 Synthesis of Asynchronous Sequential
Machines Using Verilog HDL ........................ 497
4.1 Introduction ........................................................................ 497
4.1.1 Built-In Primitive Gates ..................................... 497
4.1.2 Dataflow Modeling ............................................ 498
4.1.3 Behavioral Modeling ......................................... 498
4.1.4 Structural Modeling ........................................... 501
4.2 Synthesis Examples ............................................................ 501
4.3 Problems ............................................................................ 609
Chapter 5 Synthesis of Pulse-Mode Asynchronous
Sequential Machines Using Verilog HDL ...... 617
5.1 Introduction ........................................................................ 617
5.1.1 Built-In Primitives Gates ................................... 617
5.1.2 Dataflow Modeling ............................................ 618
5.1.3 Behavioral Modeling ......................................... 618
5.1.4 Structural Modeling ........................................... 620
5.2 Synthesis Examples ............................................................ 620
5.3 Problems ............................................................................ 687
Appendix A Event Queue ................................................... 699
Appendix B Verilog Project Procedure .............................. 715
Appendix C Answers to Select Problems .................................. 717
Chapter 1 Introduction to Verilog HDL .............................................. 717
Chapter 2 Synthesis of Synchronous Sequential Machines 1 Using
Verilog HDL ...................................................................... 743
Chapter 3 Synthesis of Synchronous Sequential Machines 2 Using
Verilog HDL ...................................................................... 767
Chapter 4 Synthesis of Asynchronous Sequential Machines Using
Verilog HDL ...................................................................... 789
Chapter 5 Synthesis of Pulse-Mode Asynchronous Sequential
Machines Using Verilog HDL ........................................... 813
Index ............................................................................................. 843