Sensing of Non-Volatile Memory Demystified

116 Pages·2019·4.604 MB·English

by  Swaroop Ghosh

Editor
Swaroop Ghosh
Sensing of
Non-Volatile
Memory
Demystified
fi
Sensing of Non-Volatile Memory Demysti ed
Swaroop Ghosh
Editor
Sensing of Non-Volatile
fi
Memory Demysti ed
123
Editor
SwaroopGhosh
Schoolof Electrical Engineering and
Computer Science
PennsylvaniaState University
State College, PA,USA
ISBN978-3-319-97345-6 ISBN978-3-319-97347-0 (eBook)
https://doi.org/10.1007/978-3-319-97347-0
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Preface
Research,development,andcommercializationofemergingnon-volatilememories
(NVMs) are being aggressively pursued by the design community to supplement
and/orsubstituteconventionalvolatileandNVmemorytechnologiesthatarefacing
stiffscalabilitychallenges.TheemergingNVMssuchasMagneticRAM(MRAM),
Spin-Transfer Torque RAM (STTRAM), Resistive RAM (RRAM) and Phase
Change Memory (PCM) are already available in market as discreet chips. It has
beenforecastedbyYolethattheemergingNVMmarketwillcontinuetogrowand
find several niche applications in health care, banking, and day-to-day computing.
One of the key aspects of the functioning of these NVMs is sensing. Since the
emerging NVMs possess better reliability and faster access latency, they are
positionedtoreplaceembeddedhigher-levelmemorysuchascache,mainmemory,
and solid-state drives (SSDs). The well-known flash sensing techniques which are
latency-intensive are not suitable for emerging NVMs. The sensing techniques for
conventional charge-based memories such as SRAM and DRAM cannot be
extended to emerging NVMs since majority of these memories are resistive in
nature. The emerging NVMs face stiff sensing challenges due to process, voltage
and temperature variations, and low operating voltage requirements. The desire to
achieve high memory density places further restrictions on sense margin. Many
conflictingdesigntrade-offsexisttomaximizethesensemarginatthecostofarea,
power, and delay. A focused treatment on the sensing challenges associated with
emerging NVMs is required to accelerate their research and development efforts.
This is a first book which covers the sensing of emerging NVMs spanning
spintronic, resistive, phase-change, and ferroelectric memory technologies.
Challenges such as shrinking margin between resistive states due to intrinsic and
extrinsicsourcesofvariations,noiseandneedfor largememorycapacityattighter
footprint,loweroperatingvoltages,andfasteraccesslatencyarediscussedindetail
in the context of sense amplifier design. Various state-of-the-art resilience
enhancement techniques are also presented. The book also investigates the impact
of application that poses new challenges and offers new opportunities for reliable
sensing.
v
vi Preface
Why a New Book
Reliablesensingisakeytoenablewiderange ofapplicationsofemergingNVMs.
The choice of memory technology determines the type of sensing technique
(current-based or voltage-based) which is drastically different from their conven-
tional memory counterparts. A multitude of interesting techniques are explored
to maximize the sense margin in the face of vanishing gap between resistance
states due to issues such as process variations. The students, industrial/academic
researchers, and practicing engineers are largely ignorant about these new
circuit-level innovations. There is lack of a book that specifically addresses the
sensingchallengesofemergingNVMs.Consideringtheimportanceofthetopic,the
book compiles outstanding contributions from prominent personalities in this area
coveringdifferentaspectsofmemory-specificsensingandvariation-tolerantdesign.
Unique Features
(cid:129) Introduction to emerging NVMs, their operating mechanisms, and features.
(cid:129) Comprehensive coverage of sensing techniques, their applications, and com-
parative analysis.
(cid:129) Comprehensive coverage of sensing challenges and techniques to overcome
those while maintaining the performance metrics.
(cid:129) A holistic view ofthe sensing solutionsthrough device-circuit co-optimization.
(cid:129) Description of emerging challenges and future research directions.
Organization and Overview of the Content
This book is organized in four chapters, each covering a major class of emerging
NVMs.Thecontentofeachchapterisdesignedtoprovidenecessarybackgroundto
the readers new in the field as well as detailed discussions on state-of-the-art
techniques for the experts in the topic.
Chapter 1 presents various classes of spintronic memory technologies, their
operatingmechanisms,andthesensingtechniques.Thecomplextrade-offsbetween
errorresiliencies,accesslatency, energy,andfootprintarealsodrawnalongwitha
comparative analysis.
Chapter 2 covers resistive RAM technology, operation, and sensing techniques
keeping both storage and non-storage applications in mind such as processing in
memory and neuromorphic computing.
Chapter 3 describes ferroelectric capacitor- and ferroelectric transistor-based
memorytechnologies andtheirsensingprinciples.Adetailedcomparative analysis
is also presented.
Preface vii
Finally, Chap. 4 presents phase-change memory technology, their operating
mechanism, and sensing principles.
Sinceseveraloftheabovememorytechnologiesfallunderresistiveclass,some
of the sensing techniques can be suitable for more than one memory technology.
Such similarities are pointed out wherever applicable to bring more clarity to the
subject.
We believe the target audience consisting of students, researchers, and industry
professionals will like the content and will be greatly benefited from it. We also
believe that the content will remain highly relevant to other classes of emerging
memoriesandalternateflavorsofthememorytechnologiesthatarecoveredinthis
book.The contentofthisbookisalso relevant for newcomputing paradigms such
as intelligent memories with computecapability and neuromorphic computing that
are drawing significant push from industry and academia.
State College, USA Swaroop Ghosh
Acknowledgements
We are very grateful to all the outstanding contributors for providing the
high-quality chapters for the book. We highly appreciate the contributors for their
wholehearted cooperation throughout this project. We also acknowledge the help
and support from the students from the LOGICS Lab. We also sincerely thank
Springer, USA, for support and all their publication materials.
We gratefully acknowledge National Science Foundation (NSF) under Grant
CNS-1722557,GrantCNS-1814710, Grant CCF-1718474, and GrantDGE-1723687,
andDARPAYoungFacultyAwardunderGrantD15AP00089forsupport.Theviews
presented in this book are author’s own and do not reflect the views of NSF and
DARPA.
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Contents
1 Sensing of Spintronic Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Behzad Zeinali and Farshad Moradi
2 Sensing of Resistive RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Qing Yang, Bonan Yan and Hai Li
3 Sensing in Ferroelectric Memories and Flip-Flops . . . . . . . . . . . . . . 47
Ahmedullah Aziz, Sandeep Krishna Thirumala, Danni Wang,
SumithaGeorge,XueqingLi,SumanDatta,VijaykrishnanNarayanan
and Sumeet Kumar Gupta
4 Sensing of Phase-Change Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Mohammad Nasim Imtiaz Khan, Alexander Jones, Rashmi Jha
and Swaroop Ghosh
Summary. .... .... .... .... ..... .... .... .... .... .... ..... .... 103
Index .... .... .... .... .... ..... .... .... .... .... .... ..... .... 105
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Editor and Contributors
About the Editor
Swaroop Ghosh (SM’13) received the B.E. (Hons.) degree from IIT Roorkee,
India,in 2000; theM.S.degree from theUniversity of Cincinnati in2004; andthe
Ph.D. degree from Purdue University in 2008. From 2016, he is an Assistant
Professor at Pennsylvania State University. Earlier, he was with the faculty of
UniversityofSouthFlorida(USF)from2012to2016.Priortothat,hewasaSenior
ResearchandDevelopmentEngineerinAdvancedDesign,IntelCorp,from2008to
2012. His research interests include next-generation circuits, cybersecurity, and
digital testing. He holds 9 patents and has published over 90 refereed papers in
this area.
He served as Associate Editor of the IEEE Transactions on Circuits and
Systems I and as Senior Editorial Board member of IEEE Journal of Emerging
Topics on Circuits and Systems (JETCAS). He has also served in the technical
program committees of ACM/IEEE conferences such as DAC, ICCAD, CICC,
DATE, ISLPED, ICCD, GLSVLSI, Nanoarch, and ISQED. He served as Program
Chair ofISQED2019andDACPh.D. Forum 2016andTrack(co)-ChairofCICC
2017–2018, ISLPED 2017–2018, and ISQED 2016–2017.
He is a recipient of Intel’s Technology and Manufacturing Group Excellence
Awardin2010,Intel’sDivisionalRecognitionAwardin2011,Intel’sDepartmental
Recognition Award in 2011 and 2012, USF Outstanding Research Achievement
Awardin2015,CollegeofEngineeringOutstandingResearchAchievementAward
in2015,DARPAYoungFacultyAward(YFA)in2015,ACMSIGDAOutstanding
New Faculty Award in 2016, YFA Director’s Fellowship in 2017, Monkowski
Early Career Award from the College of Engineering, Penn State in 2018, and
Lutron Spira Teaching Excellence Award in 2018.
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