SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

216 Pages·2007·3.92 MB·English

Converters
CHAPTER 6: CONVERTERS

INTRODUCTION 6.1
SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER
ARCHITECTURES 6.3
DIGITAL-TO ANALOG CONVERTERS (DACs OR D/As) INTRODUCTION 6.3
KELVIN DIVIDER (STRING DACs) 6.4
SEGMENTED DACs 6.5
DIGITAL POTS 6.7
THERMOMETER (FULLY DECODED) DACs 6.9
BINARY WEIGHTED CURRENT SOURCES 6.12
R-2R LADDER 6.14
MULTIPLING DACs 6.18
SEGMENTED DACs 6.20
SIGMA-DELTA DACs 6.22
I/V CONVERTERS 6.23
DIFFERENTIAL TO SINGLE-ENDED CONVERSION TECHNIQUES 6.24
SINGLE-ENDED CURRENT-TO-VOLTAGE CONVERSION 6.27
DIFFERENTIAL CURRENT-TO-VOLTAGE CONVERSION 6.27
DIGITAL INTERFACES 6.28
DATA CONVERTER LOGIC: TIMING AND OTHER ISSUES 6.33
INTERPOLATING DACs (INTERPOLATING TxDACs) 6.33
RECONSTRUCTION FILTERS 6.35
SIN(X)/(X) (SINC) 6.36
INTENTIONALLY NONLINEAR DACs 6.37
SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER
ARCHITECTURES 6.40
THE COMPARATOR: A 1-BIT ADC 6.44
SUCCESSIVE APPROXIMATION ADCs 6.45
FLASH CONVERTERS 6.50
SUBRANGING, ERROR CORRECTED, AND PIPELINED ADCs 6.52
SERIAL BIT-PER-STAGE BINARY AND GRAY CODED (FOLDING) ADCs 6.58
COUNTING AND INTEGRATING ADC ARCHITECTURES 6.64
CHARGE RUN-DOWN ADCs 6.65
RAMP RUN-UP ADCs 6.65
TRACKING ADCs 6.66
VOLTAGE-TO-FREQUENCY CONVERTERS (VFCs) 6.68
DUAL-SLOPE/MULTISLOPE ADCs 6.73
RESOLVER-TO-DIGITAL CONVERTERS (RDCs) AND SYNCHROS 6.76
BASIC LINEAR DESIGN

SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER
ARCHITECTURES (cont.)
REFERENCES 6.80
SECTION 6.3: SIGMA-DELTA (ΣΔ) CONVERTERS 6.85
HISTORICAL PERSPECTIVE 6.85
BASICS OF SIGMA-DELTA ADCs 6.90
IDLE TONE CONSIDERATIONS 6.96
HIGHER ORDER LOOP CONSIDERATIONS 6.98
MULTIBIT SIGMA-DELTA CONVERTERS 6.98
DIGITAL FILTER IMPLICATIONS 6.100
HIGH RESOLUTION MEASUREMENT SIGMA-DELTA ADCs 6.102
BAND-PASS SIGMA-DELTA CONVERTERS 6.107
SIGMA-DELTA DACs 6.108
SUMMARY 6.110
REFERENCES 6.111
SECTION 6.4: DEFINING THE SPECIFICATIONS 6.115
SECTION 6.5: DAC AND ADC STATIC TRANSFER FUNCTIONS
AND DC ERRORS 6.117
SECTION 6.6: DATA CONVERTER AC ERRORS 6.129
NOISE IN PRACTICAL ADCs 6.131
EQUIVALENT INPUT REFERRED NOISE 6.131
NOISE-FREE (FLICKER-FREE) CODE RESOLUTION 6.132
DYNAMIC PERFORMANCE OF DATA CONVERTERS 6.133
INTEGRAL AND DIFFERENTIAL NONLINEARITY DISTORTION EFFECTS 6.133
HARMONIC DISTORTION, WORST HARMONIC, TOTAL HARMONIC
DISTORTION (THD), TOTAL HARMONIC DISTORTION PLUS NOISE
(THD + N) 6.135
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD), SIGNAL-TO-NOISE
RATIO (SNR) AND EFFECTIVE NUMBER OF BITS (ENOB) 6.136
ANALOG BANDWIDTH 6.137
SPURIOUS-FREE DYNAMIC RANGE (SFDR) 6.138
TWO TONE INTERMODULATION DISTORTION (IMD) 6.141
MULTITONE SPURIOUS-FREE DYNAMIC RANGE 6.142
SECOND- AND THIRD-ORDER INTERCEPT POINTS, 1 dB COMPRESSION
POINT 6.143
WIDEBAND CDMA (W-CDMA) ADJACENT CHANNEL POWER RATIO
(ACPR) AND ADJACENT CHANNEL LEAKAGE RATIO (ADLR) 6.145
NOISE POWER RATIO (NPR) 6.146
NOISE FACTOR (F) AND NOISE FIGURE (NF) 6.149
Converters
SECTION 6.6: DATA CONVERTER AC ERRORS (cont.)
APERTURE TIME, APERTURE DELAY TIME, AND APERTURE JITTER 6.156
A SIMPLE EQUATION FOR THE TOTAL SNR OF AN ADC 6.160
ADC TRANSIENT RESPONSE AND OVERVOLTAGE RECOVERY 6.161
ADC SPARKLE CODES, METASTABLE STATES, AND BIT ERROR RATE
(BER) 6.163
DAC DYNAMIC PERFORMANCE 6.167
DAC SETTLING TIME 6.167
GLITCH IMPULSE AREA 6.168
DAC SFDR AND SNR 6.170
MEASURING DAC SNR WITH AN ANALOG SPECTRUM ANALYZER 6.172
OTHER AC SPECIFICATIONS 6.173
REFERENCES 6.175
SECTION 6.7: TIMING SPECIFICATIONS 6.177
SECTION 6.8: HOW TO READ A DATA SHEET 6.181
THE FRONT PAGE 6.181
THE SPECIFICATION TABLES 6.181
THE ABSOLUTE MAXIMUMS 6.188
THE ORDERING GUIDE 6.189
PIN DESCRIPTION 6.191
DEFINING THE SPECIFICATIONS 6.192
EQUIVALENT CIRCUITS 6.193
THE GRAPHS 6.194
THE MAIN BODY 6.198
CIRCUIT DESCRIPTION 6.198
INTERFACE 6.199
REGISTER DESCRIPTION 6.201
APPLICATIONS CIRCUITS 6.202
EVALUATION BOARDS 6.203
SUMMARY 6.203
SECTION 6.9: CHOOSING A DATA CONVERTER 6.205
DETERMINE THE PARAMETERS 6.205
PRIORITIZING THE PARAMETERS 6.206
SELECTING THE PART 6.206
BASIC LINEAR DESIGN
CONVERTERS
INTRODUCTION

CHAPTER 6: CONVERTERS

Introduction

There are two basic type of converters, digital-to-analog (DACs or D/As) and analog-to-
digital (ADCs or A/Ds). Their purpose is fairly straightforward. In the case of DACs,
they output an analog voltage that is a proportion of a reference voltage, the proportion
based on the digital word applied. In the case of the ADC, a digital representation of the
analog voltage that is applied to the ADCs input is outputted, the representation
proportional to a reference voltage.

In both cases the digital word is almost always based on a binarily weighted proportion.
The digital input or output is arranged in words of varying widths, referred to as bits,
typically anywhere from 6 bits to 24 bits. In a binarily weighted system each bit is worth
half of the bit to its left and twice the bit to its right. The greater the number of bits in the
digital word, the finer the resolution. These bits are typically arranged in groups of four,
called bytes, for convenience.

For a better understanding of the relationship between the digital domain and the analog
domain please refer to the section on sampling theory.

As stated earlier, we shall look at the operation of converters primarily from a “black
box” view. We will concern ourselves less with the internal construction of the converter
and more with its operation. We cannot, however, completely ignore the internal
architecture because in many cases it is relevant to operational advantages or limitations.
There are a number of works that cover the internal workings of the converters in much
more detail (see References).

Another point that should be kept in mind is the difference between accuracy and
resolution. The resolution of a converter is the number of bits in its digital word. The
accuracy is the number of those bits that meet the specifications. For instance, a DAC
might have 16 bits of resolution, but might only be monotonic to 14 bits. This means that
the assured accuracy of the DAC will be no better than 14 bits. Also, an audio ADC
might have a digital word width of 16 bits, but the SNR may be only 70 dB. This means
that the accuracy will only be at the 12-bit level. This is not to say that the other bits are
irrelevant. With further processing, typically filtering, often the accuracy can be
improved. While these terms are similar and sometimes used interchangeably, the
distinction between the two should be remembered.

We shall examine the DAC first.

6.1
BASIC LINEAR DESIGN

6.2
CONVERTERS
DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER
ARCHITECTURES

Digital-to-Analog Converters (DACs or D/As) Introduction

What we commonly refer to as a DAC today is typically quite a bit more. The DAC will
typically have the converter itself and a collection of support circuitry built into the chip.

The first DACs were board level designs, built from discrete components, including
vacuum tubes as the switching elements. Monolithic DACs began to appear in the early
’70s. These early examples were actually sub-blocks of the DAC. An example of this
would be the AD550, which was a 4 bit binarily weighted current source. This current
source block would be mated to a separate part, such as the AD850, which contained a
resistor array and CMOS switches. Together these would form the basic DAC. As we
moved on in time these functions were integrated on the same die, additional digital
circuitry, specifically latches to store the digital input, were added. Then a second rank of
latches was often added. The purpose of the second rank was to allow the microprocessor
or microcontroller to write to many DACs in a system and the updated them all at the
same time. The input rank of latches could also be a shift register, which would allow a
serial interface.

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6.3
BASIC LINEAR DESIGN

On the back end, since the output of the DAC is often a current, an op amp is often added
to perform the current-to-voltage (I/V) conversion. On the front end a voltage reference is
often added.

Process limitations did not allow the integration of all these sub-blocks to occur at once.
Initially, the processes used to make the various sub-blocks were not compatible. The
process that made the best switches was typically not the best for the amplifier and the
reference. As the processes became more advanced these limitations became less. Today
CMOS can make acceptable amplifiers and processes combining bipolar and CMOS
together exist.

There are several advantages to including all this additional circuitry in one package. The
first is the obvious advantage of reducing the chip count. This reduces the size of the
circuitry and increases the reliability. Probably more important is that the circuit designer
now doesn’t have to concern himself with the accuracy of several parts in a system. The
system is now one part and tested by the manufacturer as a unit.

Next we will look at the various DAC architectures. When we refer to DACs here we are
referring to the basic converter rather than the complete system.

Kelvin Divider (String DAC)

The simplest structure of all is the Kelvin divider or string DAC as shown in Figure 6.2.
An N-bit version of this DAC simply consists of 2N equal resistors in series and 2N
switches (usually CMOS), one between each node of the chain and the output. The output
is taken from the appropriate tap by closing just one of the switches (there is some slight
digital complexity involved in decoding to 1 of 2N switches from N-bit data).

This architecture is simple, has a voltage output and is inherently monotonic—even if a
resistor is accidentally short-circuited, output n cannot exceed output n + 1. It is linear if
all the resistors are equal, but may be made deliberately nonlinear if a nonlinear DAC is
required. The output is a voltage, but it has the disadvantage of having a relatively large
output impedance. This output impedance is also code dependant (the impedance changes
with changes to the digital input). In many cases it will be beneficial to follow the output
of the DAC with an op amp to buffer this output impedance and present a low impedance
source to the following circuitry.

Since only two switches operate during a transition it is a low glitch architecture (the
concept of glitch will be examined in a following section). Also, the switching glitch is
not code-dependent, making it ideal for low distortion applications. Because the glitch is
constant regardless of the code transition, the frequency content of the glitch is at the
DAC update rate and its harmonics—not at the harmonics of the DAC output signal
frequency. The major drawback of the Kelvin DAC is the large number of resistors and
switches required for high resolution. There are 2N resistors required, so a 10 bit DAC
would require 1024 switches and resistors, and as a result it was not commonly used as a
simple DAC architecture until the recent advent of very small IC feature sizes made it
very practical for low and medium resolution (typically up to 10 bits) DACs.
6.4
CONVERTERS
DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

V
REF
R
3-TO-8 3-BIT
DECODER DIGITAL
R INPUT
8
R
TO
R SWITCHES
ANALOG
OUTPUT
R
R
CIRCA 1920
R
SWITCHES WERE
RELAYS OR VACUUM TUBES
R

Figure 6.2: Simplest Voltage-Output Thermometer DAC:
The Kelvin Divider

As we mentioned in the section on sampling theory, the output of a DAC for an all 1s
code is 1 LSB below the reference, so a Kelvin divider DAC intended for use as a
general-purpose DAC has a resistor between the reference terminal and the first switch as
shown in Figure 6.2.

Segmented String DACs

A variation of the Kelvin divider is the segmented string DAC. Here we reduce the
number of resistors required by segmenting. Figure 6.3 shows two varieties of segmented
voltage-output DAC. The architecture in Figure 6.3A is sometimes called a Kelvin-
Varley Divider. Since there are buffers between the first and second stages, the second
string DAC does not load the first, and the resistors in the second string do not need to
have the same value as the resistors in the first. All the resistors in each string, however,
do need to be equal to each other or the DAC will not be linear. The examples shown
have 3-bit first and second stages but for the sake of generality, let us refer to the first
(MSB) stage resolution as M-bits and the second (LSB) as K-bits for a total of N = M +
K bits. The MSB DAC has a string of 2M equal resistors and a string of 2K equal resistors
in the LSB DAC. As an example, if we make a 10-bit string DAC out of two 5-bit
sections, each segment would have 25 or 32 resistors, for a total of 64, as opposed to the
1024 required for a standard Kelvin divider. This is an obvious advantage.

6.5
BASIC LINEAR DESIGN

(A) KELVIN-VARLEY DIVIDER (B) KELVIN DIVIDER AND
("STRING DAC") R-2R LADDER NETWORK

VREF A B A VREF OUTPUT

B

A

B
OUTPUT
A

B NOTE:
MSB OF LADDER
ON RIGHT
A

IF THE LADDER NETWORK
IS MONOTONIC, THE
B
WHOLE DAC IS

MONOTONIC
A A B

Figure 6.3: Segmented Voltage-Output DACs

Buffer amplifiers can have offset, of course, and this can cause nonmonotonicity in a
buffered segmented string DAC.

In the simpler configuration of a buffered Kelvin-Varley divider buffer (Figure 6.3A),
buffer A is always “below” (at a lower potential than) buffer B, and the extra tap labeled
“A” on the LSB string DAC is not necessary. The data decoding is just two priority
encoders.

But if the decoding of the MSB string DAC is made more complex so that buffer A can
only be connected to the taps labeled “A” in the MSB string DAC, and buffer B to the
taps labeled “B,” then it is not possible for buffer offsets to cause nonmonotonicity. Of
course, the LSB string DAC decoding must change direction each time one buffer
“leapfrogs” the other, and taps A and B on the LSB string DAC are alternately not
used—but this involves a fairly trivial increase in logic complexity and is justified by the
increased performance.

Rather than using a second string of resistors, a binary R-2R DAC can be used to
generate the three LSBs as shown in Figure 6.3B. This voltage-output DAC (Figure 6.3B)
consists of a 3-bit string DAC followed by a 3-bit buffered voltage-mode ladder network.
Again the number of resistors require for the DAC is reduced.

An unbuffered version of the segmented string DAC is shown in Figure 6.4. This version
is more clever in concept. Here, the resistors in the two strings must be equal, except that
the top resistor in the MSB string must be smaller—1/2K of the value of the others—and
the LSB string has 2K – 1 resistors rather than 2K. Because there are no buffers, the LSB
string appears in parallel with the resistor in the MSB string that it is switched across and
loads it. This drops the voltage across that MSB resistor by 1 LSB of the LSB DAC—
which is exactly what is required. The output impedance of this DAC, being unbuffered,
6.6