(SAR) ADC

37 Pages·2014·1.09 MB·English

by  Vishal Saxena

Department of Electrical and Computer Engineering
Successive Approximation ADCs
Vishal Saxena
Boise State University
([email protected])
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Successive Approximation ADC
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Data Converter Arch itectures
1 word/OSR*T
clk
1 level/T
Resolution clk
[Bits]
1 bit/T
clk
20
Partial word/T
Integrating clk
Oversampling
15
Successive Approximation
Algorithmic 1 word/T
clk
Subranging
10 Pipeline
Folding & Interpolating
Interleaving
Flash
5
Nyquist
Oversampling
0
1k 10k 100k 1M 10M 100M 1G 10G 100G
Sample Rate [Hz]
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Successive Approxim ation ADC
V
V
X
i
b
V 1
DAC
DAC . . D
. . o
. .
b
N Shift
Register
• Binary search over DAC inputs
• N*T to complete N bits
clk
• successive approximation register or SAR
• High accuracy achievable (16+ bits)
• Relies on highly accurate comparator
• Moderate speeds (typically 0.1-10 MHz parts)
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Binary Search Algor ithm
V
DAC V
i
Vi VX V
FS
b
V 1
DAC
V
DAC .. .. Do FS
. .
2
b
N Shift
Register 1 0 0 1 1 0
0 t
MSB LSB
T
clk
• DAC output gradually approaches the input voltage
• Comparator differential input gradually approaches zero
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Binary Search Algor ithm contd.
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High Performance E xample
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Charge Redistributio n SAR ADC
Φ
1e
V
X
SAR
8C 4C 2C C C
D
o
V
R
Φ Φ Φ Φ Φ
1 1 1 1 1
V
i
• 4-bit binary-weighted capacitor array DAC (aka charge scaling DAC)
• Capacitor array samples input when Φ is asserted (bottom-plate)
1
• Comparator acts as a zero crossing detector
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Charge Redistributio n (MSB)
Φ
1e
V
X
SAR
8C 4C 2C C C
D
o
V
R
Φ Φ Φ Φ Φ
1 1 1 1 1
V
i
• Start with C connected to V and others to 0 (i.e. SAR=1000)
4 R
V 8C- V 16C V
V 16C=V - V C - V C +C +C +C   V  R i  R - V
i R X 4 X 3 2 1 0 X i
16C 2
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Comparison (MSB)
V
X
1
0 t
1
Sample
MSB
V
MSB TEST : V  R  V
X i
2
• If V < 0, then V > V /2, and MSB = 1, C remains connected to V
X i R 4 R
• If V > 0, then V < V /2, and MSB = 0, C is switched to ground
X i R 4
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