Sampling Time Error Calibration for Time-Interleaved ADCs

106 Pages·2013·3.22 MB·English

by  Nandish Mehta

Sampling Time Error Calibration
for Time-Interleaved ADCs
Nandish Mehta
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Sampling Time Error Calibration for
Time-Interleaved ADCs
MASTER OF SCIENCE THESIS
For the degree of Master of Science in Microelectronics at Delft University
of Technology
Nandish Mehta
August 29,2013
FacultyofElectricalEngineering, MathematicsandComputerScience DelftUniversityof
·
Technology
Copyright ©ElectricalEngineering
Allrightsreserved.
DELFT UNIVERSITY OF TECHNOLOGY
DEPARTMENT OF
ELECTRICAL ENGINEERING
Theundersignedhereby certify thattheyhaveread and recommendto theFaculty of
Electrical Engineering,Mathematicsand ComputerScience foracceptance athesisentitled
SAMPLING TIME ERROR CALIBRATION FOR TIME-INTERLEAVED ADCS
by
NANDISH MEHTA
in partialfulfillmentoftherequirementsforthedegreeof
MASTER OF SCIENCE MICROELECTRONICS
Dated: August29,2013
Supervisor(s):
dr. Frank vanderGoes
dr. KlaasBult
prof. dr. KofiA. A. Makinwa
Reader(s):
dr.ir.MichielPertijs
dr. ing. LeodeVreede

Abstract
Inthisthesisthedesignofthetimingerrorcalibration loopforatime-interleaved ADCisdescribed.
The realization of fully-digital radio transceiver requires a wideband capture ADC that can si-
multaneously capture all the commercial wireless bands present in a mobile handset. These ADCs
are expected to operate at GHz sampling speed with good energy efficiency. Both of these con-
tradicting requirements can be fulfilled by employing time-interleaved architecture. Unfortunately,
time-interleaved ADCs suffer from interleaving issues like mismatch in sampling time error. These
issuescanbeaddressed bydesigning adedicated calibration loop.
In this thesis an attempt is made to design a calibration loop that detects and corrects the sam-
pling timeerrors withhigh precision. Thetiming error detection technique relies onintroducing two
additional reference ADCs. The correction of timing errors is done using the least mean square it-
erative algorithm (LMS). Convergence and stability of such calibration loops are extremely critical.
Hence, they are exhaustively investigated in this thesis. Factors that hamper the loop convergence
were identified and relevant solutions are applied to overcome them. Furthermore, it was found that
the loading effect of the reference ADCs greatly affects the accuracy of the timing error detection.
A simple solution using delay lines is shown to remove this effect. Finally, techniques like inserting
dummysamplingcircuits,scalingsamplingcapacitance, andmatchingtheclock-paths, areemployed
toachievetimingerrorcorrection accuracyintheorderof5fslevel.
Some of these techniques are implemented at the architecture level, whereas some are imple-
mented at circuit level. The effectiveness of the architecture level techniques is verified through
MATLAB modeling while the circuit level techniques are verified through circuit simulations. The
sub-blocksforthecalibrationlooparedesignedinindustrial28nmCMOSprocessandrelevantsimu-
lationresultsarepresented. Circuitslike11-bit10µWDACwith0.6LSBDNL,atrack-and-hold with
HD of 72dB at 1GHz input frequency, and clock-path with a mean delay of 11ps, are designed for
3
thetimingerrorcalibration loop.
Keywords: LMS calibration loop, Timing error detection, Time-interleaving, Observer Effect,
Referencelanes,Wideband captureADC,Digital-to-Analog converter, Track-and-hold, Low-power.
MasterofScienceThesis NandishMehta
ii
NandishMehta MasterofScienceThesis
Table of Contents
1 Introduction 1
1-1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1-2 BasicsofTime-Interleaved ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1-3 Application: Wideband CaptureADC . . . . . . . . . . . . . . . . . . . . . . . . . 5
1-4 TargetTimingErrorCorrection Accuracy . . . . . . . . . . . . . . . . . . . . . . . 7
1-5 ResearchGoalandContributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1-6 ThesisOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 SamplingTimeErrors in Time-InterleavedA/DConverters 11
2-1 BasicsofTime-Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2-2 TypesofInterleaving Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2-2-1 OffsetMismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2-2-2 GainMismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2-2-3 TimingMismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2-2-3-1 ImpactofTimingError . . . . . . . . . . . . . . . . . . . . . . . 17
2-2-3-2 SourcesofTimingMismatch . . . . . . . . . . . . . . . . . . . . 18
2-2-4 BandwidthMismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2-3 TimingErrorDetectionandCalibration . . . . . . . . . . . . . . . . . . . . . . . . 20
2-3-1 Useofcommonsample-and-hold. . . . . . . . . . . . . . . . . . . . . . . . 21
2-3-2 Foreground vsbackground calibration. . . . . . . . . . . . . . . . . . . . . 21
2-3-3 Digitaldetection anddigitalcorrection oftimingerrors. . . . . . . . . . . . 22
2-3-4 Digitaldetection andanalogcorrection oftimingerrors. . . . . . . . . . . . 23
2-4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MasterofScienceThesis NandishMehta
iv TableofContents
3 Timing ErrorCalibrationLoop 25
3-1 PrincipleofOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3-2 Description ofCalibration Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-3 Convergence oftheCalibration Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3-3-1 InputSignalStatistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3-3-2 Gainmismatchandoffsetofthetworeference lanes . . . . . . . . . . . . . 30
3-3-3 LimitonSpeedofConvergence . . . . . . . . . . . . . . . . . . . . . . . . 32
3-4 StabilityofCalibration Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3-5 ImpactofFiniteQuantization ofthetwoReferenceLanes . . . . . . . . . . . . . . . 34
3-6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Sampling-TimeError Dueto ObserverEffectofReferencelanes 37
4-1 ObserverEffect: SimpleRCModelAnalysis . . . . . . . . . . . . . . . . . . . . . . 38
4-2 ObserverEffect: SamplingInstanceInteractions . . . . . . . . . . . . . . . . . . . . 40
4-3 Isolating theSamplingInteractions usingaWireDelay . . . . . . . . . . . . . . . . 42
4-4 MismatchbetweenDummylaneandREFlane . . . . . . . . . . . . . . . . . . . . 44
4-5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 Circuit Implementation 51
5-1 System-LevelDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5-2 ClockPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5-2-1 Clock-Phase generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5-2-2 SamplingEdgeTuningCircuit . . . . . . . . . . . . . . . . . . . . . . . . . 53
5-3 Track-and-hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5-4 HOLDBufferDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5-5 Digital-to-Analog Converter(DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5-5-1 EstimatingDynamicRange . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5-5-2 CircuitImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5-5-3 SimulationofDNL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5-5-4 DesignSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5-6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 Conclusion 71
6-1 ProblemDefinition: ARecap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6-2 Thesiscontribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6-3 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
A TargetSpecifications 75
B MATLABCodeto SimulateBasicInterleavingIssues 77
C Simulation Setupfor TimingErrors 81
C-1 CoherentFFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
C-2 SettingUpVariables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
NandishMehta MasterofScienceThesis