Table Of Content

Safety Manual for RM57x Hercules ARM Safety MCUs User's Guide LiteratureNumber:SPNU575A May2014–RevisedSeptember2016 Contents 1 Introduction ........................................................................................................................ 8 2 HerculesRM57xProductOverview....................................................................................... 10 2.1 TargetedApplications.................................................................................................. 11 2.2 ProductSafetyConstraints............................................................................................ 12 3 HerculesDevelopmentProcessforManagement ofSystematicFaults..................................... 13 3.1 TIStandardMCUAutomotiveDevelopmentProcess ............................................................. 14 3.2 TIMCUAutomotiveLegacyIEC61508DevelopmentProcess.................................................. 15 3.3 YogitechfRMethodologyDevelopmentProcess ................................................................... 15 3.4 HerculesEnhancedSafetyDevelopmentProcess................................................................. 15 4 HerculesProductArchitectureforManagement ofRandomFaults........................................... 18 4.1 SafeIslandPhilosophyandArchitecturePartitiontoSupportSafetyAnalysis(FMEA/FMEDA) ............ 18 4.2 IdentificationofParts/Elements....................................................................................... 19 4.3 ManagementofFamilyVariants...................................................................................... 20 4.4 OperatingStates........................................................................................................ 20 4.5 ManagementofErrors................................................................................................. 22 5 SystemIntegratorRecommendations................................................................................... 23 5.1 SystemIntegratorActivities........................................................................................... 23 5.2 HintsforPerformingDependent/CommonCauseFailureAnalysisIncludingtheHerculesMCU........... 25 5.3 HintsforImprovingIndependenceofFunction/Co-ExistenceofFunctionWhenUsingtheHerculesMCU 25 5.4 SupportforSystemIntegratorActivities............................................................................. 25 6 BriefDescriptionofElements.............................................................................................. 26 6.1 PowerSupply........................................................................................................... 26 6.2 PowerManagementModule(PMM)................................................................................. 26 6.3 Clocks.................................................................................................................... 27 6.4 Reset..................................................................................................................... 27 6.5 SystemControlModule................................................................................................ 28 6.6 ErrorSignalingModule(ESM) ....................................................................................... 29 6.7 CPU Subsystem........................................................................................................ 29 6.8 PrimaryEmbeddedFlash ............................................................................................. 31 6.9 FlashEEPROMEmulation(FEE).................................................................................... 32 6.10 PrimaryEmbeddedSRAM............................................................................................ 33 6.11 CPUInterconnectSubsystem......................................................................................... 34 6.12 PeripheralInterconnectSubsystem.................................................................................. 35 6.13 PeripheralCentralResource1(PCR1).............................................................................. 35 6.14 PeripheralCentralResource2(PCR2).............................................................................. 36 6.15 PeripheralCentralResource3(PCR3).............................................................................. 36 6.16 EFuseStaticConfiguration............................................................................................ 37 6.17 OTPStaticConfiguration.............................................................................................. 37 6.18 I/OMultiplexingModule(IOMM)...................................................................................... 38 6.19 VectoredInterruptModule(VIM)..................................................................................... 38 6.20 RealTimeInterrupt(RTI).............................................................................................. 39 2 TableofContents SPNU575A–May2014–RevisedSeptember2016 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated www.ti.com 6.21 DirectMemoryAccess(DMA) ........................................................................................ 40 6.22 High-EndTimer(N2HET),HETTransferUnit(HTU).............................................................. 40 6.23 Multi-BufferedAnalog-to-DigitalConverter(MibADC)............................................................. 42 6.24 EnhancedPulseWidthModulators(ePWM)........................................................................ 42 6.25 EnhancedCapture(eCAP)............................................................................................ 43 6.26 EnhancedQuadratureEncoderPulse(eQEP)..................................................................... 44 6.27 MultiBufferedSerialPeripheralInterface(MibSPI)................................................................ 45 6.28 Inter-IntegratedCircuit(I2C) .......................................................................................... 46 6.29 SerialCommunicationInterface(SCI)............................................................................... 46 6.30 LocalInterconnectNetwork(LIN) .................................................................................... 47 6.31 ControllerAreaNetwork(DCAN)..................................................................................... 48 6.32 General-PurposeInput/Output(GIO)................................................................................ 49 6.33 Ethernet.................................................................................................................. 49 6.34 ExternalMemoryInterface(EMIF)................................................................................... 50 6.35 JTAGDebug,Trace,Calibration,andTestAccess................................................................ 51 6.36 Cortex-R5FCentralProcessingUnit(CPU)DebugandTrace................................................... 51 6.37 DataModificationModule(DMM)..................................................................................... 51 6.38 RAMTracePortInterface(RTP)..................................................................................... 51 6.39 ParameterOverlayModule(POM)................................................................................... 52 6.40 ErrorProfilingController(EPC)....................................................................................... 52 6.41 TemperatureSensor................................................................................................... 53 7 BriefDescriptionofDiagnostics........................................................................................... 54 7.1 1oo2SoftwareVotingUsingSecondaryFreeRunningCounter................................................. 54 7.2 BitErrorDetection...................................................................................................... 54 7.3 BitMultiplexinginFEEMemoryArray............................................................................... 54 7.4 BitMultiplexinginFlashMemoryArray.............................................................................. 54 7.5 BitMultiplexinginPrimarySRAMMemoryArray................................................................... 54 7.6 BitMultiplexinginPeripheralSRAMMemoryArray................................................................ 54 7.7 CPUIllegalOperationandInstructionTrapping ................................................................... 55 7.8 LogicBuiltInSelf-Test(LBIST) ...................................................................................... 55 7.9 LogicBuiltInSelf-Test(LBIST)Auto-Coverage.................................................................... 56 7.10 CPULockstepCompare .............................................................................................. 56 7.11 VIMLockstepCompare ............................................................................................... 56 7.12 LockstepComparatorSelf-Test....................................................................................... 56 7.13 CPUOnlineProfilingUsingthePerformanceMonitoringUnit.................................................... 56 7.14 CPUMemoryProtectionUnit(MPU)................................................................................. 57 7.15 CRCAuto-coverage.................................................................................................... 57 7.16 CRCinMessage........................................................................................................ 57 7.17 DCANAcknowledgeErrorDetection................................................................................. 57 7.18 DCANFormErrorDetection .......................................................................................... 57 7.19 DCANStuffErrorDetection........................................................................................... 57 7.20 DCANProtocolCRCinMessage..................................................................................... 57 7.21 DisabletheDMMPinInterface....................................................................................... 58 7.22 DisabletheRTPPinInterface........................................................................................ 58 7.23 DualClockComparator(DCC)........................................................................................ 58 7.24 AutoloadSelf-Test...................................................................................................... 58 7.25 EfuseAutoloadSelf-TestAuto-Coverage........................................................................... 58 7.26 EFuseECC.............................................................................................................. 58 7.27 EFuseECCLogicSelf-Test........................................................................................... 58 SPNU575A–May2014–RevisedSeptember2016 Contents 3 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated www.ti.com 7.28 eQEPQuadratureWatchdog.......................................................................................... 58 7.29 eQEPSoftwareTestofQuadratureWatchdogFunctionality..................................................... 59 7.30 ErrorTrapping-IOMM................................................................................................. 59 7.31 ErrorTrapping(includingPeripheralSlaveErrorTrapping)-L2/L3Interconnect.............................. 59 7.32 EthernetAlignmentErrorDetection.................................................................................. 59 7.33 EthernetPhysicalLayerFault ........................................................................................ 59 7.34 ExternalMonitoringofWarmReset(nRST) ........................................................................ 59 7.35 ExternalMonitoringviaECLK......................................................................................... 59 7.36 ExternalVoltageSupervisor........................................................................................... 60 7.37 ExternalWatchdog..................................................................................................... 60 7.38 FEEContentsCheckbyHardwareCRC............................................................................ 60 7.39 FEEDataECC.......................................................................................................... 60 7.40 FEESectorProtection................................................................................................. 60 7.41 FlashAddressandControlBusParity............................................................................... 61 7.42 FlashContentsCheckbyHardwareCRC........................................................................... 61 7.43 FlashECC............................................................................................................... 61 7.44 FlashHardErrorCacheandLivelock................................................................................ 61 7.45 FlashSectorProtection................................................................................................ 62 7.46 FlashWrapperAddressECC......................................................................................... 62 7.47 FlashWrapperDiagMode5Test.................................................................................... 62 7.48 FlashWrapperDiagMode7Test.................................................................................... 62 7.49 GlitchFilteringonnRSTandnPORRST ............................................................................ 62 7.50 HardwareCRCCheckofExternalMemory......................................................................... 62 7.51 HardwareCRCCheckofOTPContents............................................................................ 62 7.52 HardwareDisableofJTAGPort...................................................................................... 62 7.53 InformationRedundancyTechniques................................................................................ 63 7.54 InformationRedundancyTechniques-CPUSpecific ............................................................. 63 7.55 InformationRedundancyTechniques-DCANSpecific............................................................ 63 7.56 InformationRedundancyTechniques-DMASpecific............................................................. 63 7.57 InformationRedundancyTechniques-N2HETSpecific.......................................................... 63 7.58 InternalVoltageMonitor(VMON) .................................................................................... 64 7.59 InternalWatchdog...................................................................................................... 64 7.60 IOMMMasterIDFiltering.............................................................................................. 64 7.61 LINChecksumErrorDetection ....................................................................................... 64 7.62 LINNo-ResponseErrorDetection.................................................................................... 64 7.63 LINPhysicalBusErrorDetection..................................................................................... 65 7.64 LIN/SCIBitErrorDetection.......................................................................................... 65 7.65 LIN/SCIFrameErrorDetection ..................................................................................... 65 7.66 LIN/SCIOverrunErrorDetection.................................................................................... 65 7.67 LockingMechanismforControlRegisters........................................................................... 65 7.68 LockoutofJTAGAccessUsingAJSM............................................................................... 65 7.69 LowPowerOscillatorClockDetector(LPOCLKDET).............................................................. 65 7.70 MemoryProtectionUnit(MPU)forNon-CPUBusMasters ...................................................... 65 7.71 MibADCCalibration.................................................................................................... 66 7.72 MibADCInformationRedundancyTechniques..................................................................... 66 7.73 MibADCInputSelf-Test................................................................................................ 66 7.74 MibSPI/SPIDataLengthErrorDetection............................................................................ 66 7.75 MibSPI/SPIDataOverrunDetection................................................................................. 66 4 Contents SPNU575A–May2014–RevisedSeptember2016 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated www.ti.com 7.76 MibSPI/SPISlaveDesyncDetection................................................................................. 66 7.77 MibSPI/SPISlaveTimeoutDetection................................................................................ 66 7.78 MonitoringbySecondN2HET........................................................................................ 67 7.79 MonitoringbyeCAPorN2HET....................................................................................... 67 7.80 Non-PrivilegedBusMasterAccess .................................................................................. 67 7.81 OTPAutoloadECC..................................................................................................... 67 7.82 ParityinMessage....................................................................................................... 67 7.83 PeriodicHardwareCRCCheckofOTPContents.................................................................. 67 7.84 PCRAccessManagement:ProtectionModeandMasterIDFiltering............................................ 67 7.85 PeriodicHardwareCRCCheckofSRAMContents................................................................ 68 7.86 PeriodicSoftwareReadBackofStaticConfigurationRegisters ................................................ 68 7.87 PeripheralSRAMParity................................................................................................ 68 7.88 PeripheralMemoryECC............................................................................................... 68 7.89 PLLSlipDetector....................................................................................................... 68 7.90 PrimarySRAMAddressandControlBusParity.................................................................... 68 7.91 PrimarySRAMDataandECCStorageinMultiplePhysicalBanksperLogicalAddress..................... 69 7.92 PrimarySRAMCorrectableECCProfiling .......................................................................... 69 7.93 ECConCacheRAM................................................................................................... 69 7.94 PrimarySRAMDataECC............................................................................................. 69 7.95 PrimarySRAMWrapperRedundantAddressDecode............................................................ 69 7.96 PrimarySRAMHardErrorCacheandLivelock.................................................................... 70 7.97 PrivilegedModeAccessandMulti-BitEnableKeysforControlRegisters...................................... 70 7.98 PBISTCheckofPrimaryorModuleSRAM......................................................................... 70 7.99 PBISTAuto-coverage.................................................................................................. 71 7.100 PowerDomainInactivityMonitor..................................................................................... 71 7.101 PBISTTestofParityBitMemory..................................................................................... 71 7.102 PBISTTestofECCBitMemory...................................................................................... 71 7.103 LockstepPSCON....................................................................................................... 71 7.104 RedundantAddressDecodeSelf-Test.............................................................................. 71 7.105 RedundantTemperatureSensors.................................................................................... 71 7.106 ScrubbingofSRAMtoCorrectDetectedSingleBitErrors....................................................... 71 7.107 ShadowRegisters...................................................................................................... 72 7.108 SoftwareCheckofCauseofLastReset ........................................................................... 72 7.109 SoftwareReadBackofCPURegisters............................................................................. 72 7.110 SoftwareReadBackofWrittenConfiguration...................................................................... 72 7.111 SoftwareTestofDCCFunctionality ................................................................................. 72 7.112 SoftwareTestofDWDFunctionality................................................................................. 72 7.113 SoftwareTestofDWWDFunctionality.............................................................................. 72 7.114 SoftwareTestofECCProfiler(EPC)................................................................................ 72 7.115 SoftwareTestofErrorPathReporting .............................................................................. 72 7.116 SoftwareTestofFlashSectorProtectionLogic.................................................................... 72 7.117 SoftwareTestofFunctionIncludingErrorTests................................................................... 73 7.118 SoftwareTestofFunctionUsingI/OLoopback.................................................................... 73 7.119 SoftwareTestofFunctionUsingI/OCheckingInGIOMode.................................................... 73 7.120 SoftwareTestofFunctionUsingI/OLoopbackinTransceiver/PHY ........................................... 73 7.121 SoftwareTestofFunctionUsingI/OLoopbackIncludingErrorTests-IOMMOnly.......................... 73 7.122 SoftwareTestofHardwareCRC..................................................................................... 73 7.123 SoftwareTestofMPUFunctionality................................................................................. 74 7.124 SoftwareTestofParityLogic......................................................................................... 74 SPNU575A–May2014–RevisedSeptember2016 Contents 5 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated www.ti.com 7.125 SoftwareTestofPBIST ............................................................................................... 74 7.126 SoftwareTestofSRAMWrapperAddressDecodeDiagnosticandECC...................................... 74 7.127 SoftwareTestforReset............................................................................................... 74 7.128 SoftwareWarmResetGeneration................................................................................... 74 7.129 TransmissionRedundancy............................................................................................ 74 7.130 UseofCoreSightDebugLogicKeyEnableScheme.............................................................. 74 7.131 UseofDCCasProgramSequenceWatchdog..................................................................... 74 7.132 UseofMPUstoBlockAccesstoMemoryMappedDebug....................................................... 75 7.133 ExecutionofInterconnectSelf-Test.................................................................................. 75 7.134 CPUInterconnectHardwareChecker............................................................................... 75 7.135 TimeoutMonitoringonTheBusTransaction....................................................................... 75 7.136 TransactionECC(DataLines) ....................................................................................... 75 7.137 TransactionParity(AddressandControlLines) ................................................................... 76 7.138 PeripheralInterconnectNewMemoryProtectionUnit(NMPU).................................................. 76 7.139 SoftwareTestofTheNewMemoryProtectionUnit(NMPU)Functionality..................................... 76 7.140 SoftwareTestofECCLogic.......................................................................................... 76 7.141 Multi-BitKeyedSelf-CorrectableHigh-IntegrityBits............................................................... 76 8 NextStepsinYour SafetyDevelopment................................................................................ 77 AppendixA SummaryofSafetyFeatureUsage.............................................................................. 78 AppendixB DevelopmentInterfaceAgreement............................................................................ 125 B.1 AppointmentofSafetyManagers.................................................................................. 125 B.2 TailoringoftheSafetyLifecycle.................................................................................... 125 B.3 ActivitiesPerformedbyTI.......................................................................................... 127 B.4 InformationtobeExchanged....................................................................................... 128 B.5 PartiesResponsibleforSafetyActivities ......................................................................... 128 B.6 CommunicationofTargetValues.................................................................................. 129 B.7 SupportingProcessesandTools.................................................................................. 129 B.8 SupplierHazardandRiskAssessment........................................................................... 129 B.9 CreationofFunctionalSafetyConcept ........................................................................... 129 AppendixC RevisionHistory ..................................................................................................... 130 6 Contents SPNU575A–May2014–RevisedSeptember2016 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated www.ti.com List of Figures 1 DeviceRevisionCodeIdentification....................................................................................... 8 2 HerculesProductArchitectureOverview................................................................................ 10 3 TIStandardMCUAutomotiveQMDevelopmentProcess............................................................ 14 4 HerculesEnhancedFunctionalSafetyDevelopmentProcess....................................................... 17 5 PartitionofHerculesMCUforSafetyAnalysis......................................................................... 18 6 OperatingStatesoftheHerculesMCU ................................................................................. 21 7 LockstepTemporalDiversity.............................................................................................. 30 8 HerculesTailoringofSafetyLifecycle.................................................................................. 126 List of Tables 1 IdentificationofParts/Elements .......................................................................................... 19 2 SummaryofESMErrorIndication....................................................................................... 22 3 KeytoSummaryofSafetyFeaturesandDiagnostics................................................................. 78 4 SummaryofSafetyFeaturesandDiagnostics ........................................................................ 79 5 ActivitiesPerformedbyTIvs.PerformedbySEooCCustomer.................................................... 127 6 ProductSafetyDocumentation.......................................................................................... 128 7 ProductFunctionalDocumentationtobeConsideredinSafety-RelatedDesign................................. 128 8 ProductSafetyDocumentationToolsandFormats.................................................................. 129 9 SPNU575ARevisions.................................................................................................... 130 SPNU575A–May2014–RevisedSeptember2016 ListofFigures 7 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated User's Guide SPNU575A–May2014–RevisedSeptember2016 Safety Manual for RM57x Hercules ARM Safety MCUs 1 Introduction You,asystemandequipmentmanufacturerordesigner,areresponsibletoensurethat yoursystems(and anyTI hardwareorsoftwarecomponentsincorporatedinyoursystems)meetallapplicablesafety, regulatory,andsystem-levelperformancerequirements.Allapplicationandsafetyrelatedinformationin thisdocument(includingapplicationdescriptions,suggestedsafetymeasures,suggestedTIproducts,and othermaterials)isprovidedforreferenceonly.Youunderstandandagreethat youruseofTIcomponents insafetycriticalapplicationsisentirelyatyourrisk,andthat you(asbuyer)agreetodefend, indemnify, andholdharmlessTIfromanyandalldamages,claims, suits,orexpenseresultingfromsuchuse. ThisdocumentisasafetymanualfortheTexasInstrumentsHerculessafetycriticalmicrocontroller product family.Theproductfamilyutilizesacommon safetyarchitecturethat isimplementedinmultiple applicationfocusedproducts.Productconfigurationssupportedbythissafetymanualincludesilicon revisionsAandBofthefollowingproducts: (Notethat thepartnumberslistedbelowarefor revisionB; otherrevisionsareslightlydifferent.Thedevicerevisioncanbedeterminedbythesymbolsmarkedon the topofthedeviceasseeninFigure1belowthislist). • RM4xxSafetyCriticalMicrocontrollers – RM57L843-ZWT(OrderablePart#:RM57L843BZWTT) – RM57L843-ZWT(OrderablePart#:RM57L843BZWTTR) RM57L 843BZWTT ##B-####### G1 __ Device Revision Code Figure1.DeviceRevisionCodeIdentification ThisSafetyManualprovidesinformationneededbysystemdeveloperstoassistinthecreationofasafety criticalsystemusingasupportedHerculesmicrocontroller.Thisdocumentcontains: • Anoverview ofthesupersetproductarchitecture • Anoverview ofthedevelopmentprocessutilizedtoreducesystematicfailures • Anoverview ofthesafetyarchitecturefor managementofrandomfailures • Thedetailsofarchitecturepartitions,implementedsafetymechanisms SafeTIisatrademarkofTexasInstruments. ARM,CortexareregisteredtrademarksofARMLimited. AdobeisatrademarkofAdobeSystemsIncorporatedintheUnitedStates,and/orothercountries. IBM,DOORSareregisteredtrademarksofInternationalBusinessMachinesCorporation,registeredinmanyjurisdictionsworldwide. Microsoft,ExcelareregisteredtrademarksofMicrosoftCorporationintheUnitedStatesand/orothercountries,orboth. Allothertrademarksarethepropertyoftheirrespectiveowners. 8 SafetyManualforRM57xHerculesARMSafetyMCUs SPNU575A–May2014–RevisedSeptember2016 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated www.ti.com Introduction Thefollowinginformationisdocumentedinthe SafetyAnalysisReportSummaryfor RM57xARM®-Based SafetyCriticalMicrocontrollers(SPNU578) andisnotrepeatedinthisdocument: • SummaryoffailureratesoftheMCUestimatedatthechiplevel • Assumptionsofuseutilizedincalculationofsafetymetrics • Summaryoftargetedstandard(IEC61508,ISO26262,andsoforth)safetymetricsatthechip level Thefollowinginformationisdocumentedinthe DetailedSafetyAnalysisReportfor RM57xARM®-Based SafetyCriticalMicrocontrollers(SPNU579) andisnotrepeatedinthisdocument: • Fault modelusedtoestimatedevicefailureratessuitabletoenablecalculationofcustomizedfailure rates • QuantitativeFMEA(alsoknownasFMEDA, FailureModes,Effects, andDiagnosticsAnalysis)with detailtothesub-modulelevelofthedevice, suitabletoenablecalculationbasedoncustomized applicationofdiagnostics Thefollowinginformationisdocumentedinthe SafetyReport,andwillnotberepeatedinthisdocument: • Resultsofassessmentsofcompliancetotargetedstandards TheuserofthisdocumentshouldhaveageneralfamiliaritywiththeHerculesproductfamilies.Formore information,seehttp://www.ti.com/hercules.Thisdocumentisintendedtobeusedinconjunction withthe pertinentdatasheets,technicalreferencemanuals,andotherdocumentationfor theproductsunder development. Forinformationwhichisbeyondthescopeofthelisteddeliverables,pleasecontact yourTIsales representativeorhttp://www.ti.com. SPNU575A–May2014–RevisedSeptember2016 SafetyManualforRM57xHerculesARMSafetyMCUs 9 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated HerculesRM57xProductOverview www.ti.com 2 Hercules RM57x Product Overview TheRM57x65nmHerculesproductfamilyisanevolutionoftheprovenTMS570LSHerculesproductsin the65nmmanufacturingprocess.Asimplified graphicalviewoftheproduct superset architecture can be seeninFigure2.Thisisabasicrepresentationofthearchitectureandisnotallinclusive. Forexample, productsinthefamilymayscalebasedonthenumberofperipherals,numberofbusmaster peripherals, oramountofmemory-buttheprogrammer'smodelremainsconsistent. Level One Hierarchy Cortex R5F CPU Cluster Low Latency Peripheral Port Level Two Hierarchy Level Two Level Two CPU Slave CPU Master Bus Master Bus Master Bus Master Debug Bus General Peripheral Peripheral Peripheral Master DMA CPU Interconnect Peripheral Interconnect CRC CRC Flash External SRAM Flash Emulated Memory EEPROM Interface Level Three Hierarchy 1 n Peripheral e Peripheral Peripheral e Peripheral c c ur ur o o s s e e R R al al Peripheral ntr Peripheral Peripheral ntr Peripheral e e C C al al er er h h p p Peripheral eri Peripheral Peripheral eri Peripheral P P Figure2.HerculesProductArchitectureOverview 10 SafetyManualforRM57xHerculesARMSafetyMCUs SPNU575A–May2014–RevisedSeptember2016 SubmitDocumentationFeedback Copyright©2014–2016,TexasInstrumentsIncorporated

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Safety Manual for RM57x Hercules ARM Safety. MCUs. User's Guide. Literature Number: SPNU575A. May 2014–Revised September 2016
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Safety Manual for RM57x Hercules ARM Safety. MCUs. User's Guide. Literature Number: SPNU575A. May 2014–Revised September 2016

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