Table Of ContentRobust SRAM Designs and Analysis
Jawar Singh • Saraju P. Mohanty (cid:129) Dhiraj K. Pradhan
Robust SRAM Designs
and Analysis
123
JawarSingh SarajuP.Mohanty
IndianInstituteofInformationTechnology UniversityofNorthTexas
DesignandManufacturing DiscoveryPark,3940N.Elm,
DumnaAirportRoad RoomF247
Jabalpur Denton
India USA
DhirajK.Pradhan
UniversityofBristol
MerchantVenturersBuilding
WoodlandRd.
Bristol
UnitedKingdom
ISBN978-1-4614-0817-8 ISBN978-1-4614-0818-5(eBook)
DOI10.1007/978-1-4614-0818-5
SpringerNewYorkHeidelbergDordrechtLondon
LibraryofCongressControlNumber:2012936831
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JawarSinghdedicatedthisworkto his
grandmotherNarayniDevi andgrandfather
lateshriKehariSingh
SarajuP.Mohantywould liketo dedicatethis
worktoUma, parents,andsisters.
DhirajK. Pradhanwouldliketodedicatethis
worktohisfamily
Preface
During the past decades, Complementary Metal Oxide Semiconductor (CMOS)
technology has emerged as the dominant fabrication method and became the
exclusivechoiceforsemiconductormemories.Particularly,StaticRandomAccess
Memories(SRAMs)thatplayasignificantroleinthememoryhierarchyofamodern
computer system and continue to be a critical component across wide range of
microelectronicsapplicationsfrom consumer wireless to high performanceserver
processors, multimedia and System-on-Chip (SoC) products. SRAM bitcells in
generalaremadeofminimumgeometrydevicesforhighdensitytokeeppacewith
CMOStechnologyscaling;as a result, theyare thefirst to sufferfromtechnology
scalinginducedsideeffects.Therefore,severalalternateSRAMbitcellcircuitsand
architectureshaverecentlybeenproposedtomeetthenano-regimechallengessuch
aslow-power,processvariationandsofterrors.Emphasisisalsogivenonalternate
devicessuch asTunnelField EffectTransistors(TFETs)based SRAM bitcellsfor
lowpowerapplications.
The objective of this book is to provide a systematic and comprehensive
insight which aids the understanding of SRAM bitcell circuits, architectures, and
design and analysis techniques. The nano-regime challenges such as low-power,
process variation and soft errors are the core issues considered while designing
and analyzing the SRAM bitcells in depth. Robust SRAM designs and analysis
techniquesshowcircuitandembeddedsystemdesigners,researchers,andengineers
variousaspectofdesignandanalysisofSRAMbitcellcircuitsandarrays.Theabove
conceptsare furtherelaboratedto providein depthguidancetolargecachedesign
neededinembeddedandportablesystems.Thetextprovidesalternativetopologies
tosix-transistor(6T)SRAMwhicharemorerobustwhenimplementedusingstate-
of-the-artnano-scaleCMOStechnology.Topologiesforlow-powerSRAMbitcells
areclassifiedonthebasisoftheirrobustnessandelaboratedalongwiththeirmerits
and de-merits. Various quality metrics are discussed to meet the small and large
sizedcachememories.
The content of this book is directed to nano-scale VLSI design engineers,
graduatestudentsin electricalengineering,and computerscientists who are about
to start their research in SRAM design. It is an important source for engineers
vii
viii Preface
who intended to develop and understandthe differentaspects of SRAM. The text
assumedthatreadershavebasicknowledgeandfamiliaritywithelectroniccircuits
anddevices.ThegoalofthisbookistotraintheVLSIdesignengineersandstudents
todesignSRAMandcachearchitecturerationally.
This book provides a sufficient amount of fundamentals to become familiar
with the terminologyof the SRAM design and analysis. The main objective is to
achieve in depth knowledge in few topics such as operation, design and analysis
of CMOS and TFET based SRAMs. The book is organized in six chapters:
(1) Introduction to SRAM, (2) Design Metrics of SRAM Bitcell, (3) Single-
endedSRAM Bitcell Design,(4) 2-PortSRAM Bitcell Design, (5)SRAM Bitcell
Design using UnidirectionalDevices, and (6) NBTI and its effecton SRAM. The
introductory description of the SRAM serves as a basis for understanding the
importance of SRAM in memory hierarchyand need of basic building blocks for
therealizationofcachememories.Basicoperationsandstaticanddynamicstability
analysis for small and large sized caches show how conventionalmethods do not
provide adequate data points for stability analysis. Case study of single-ended
six-transistor and 2-port SRAM bitcells based cache modules show the complete
designflowofSRAMs.TheimplicationsinrealizingofSRAMusingunidirectional
devicessuchasTFETsarestudiedindetailsandtwodifferentSRAMbitcellsusing
TFETs are compared with standard six-transistor CMOS SRAM bitcell. Finally,
theimpactofNegativeBias TemperatureInstabilityisstudiedondifferentSRAM
configurations.
Authorsofthisbookaregratefultoallthepeoplewithoutwhomtheworkcould
not have been accomplished. Saraju P. Mohanty will like to acknowledge Dean
College of Engineeringat UNT. He will acknowledgeCSE departmentchairman,
colleagues,andstafffortheirsupport.Hewillliketoacknowledgeallhispastand
currentstudents.
Authors would like to thank invaluable support from our families during the
preparationofthisbook.JawarSinghwouldliketoexpresshisappreciationtohis
wifeJyoti,theirdaughterJeevikaandsonSiyonfortheirunderstandingandsupport.
SarajuP.MohantywouldliketoexpressthankstoUma,parents,andsisters.
JawarSingh
SarajuP.Mohanty
DhirajK.Pradhan
Contents
1 IntroductiontoSRAM ...................................................... 1
1.1 CMOSTechnologyScaling............................................. 1
1.2 WhySRAM?............................................................ 2
1.3 SRAMArchitecture..................................................... 5
1.3.1 SRAMBitcell................................................... 6
1.3.2 AddressDecoders............................................... 7
1.3.3 PrechargeCircuit ............................................... 8
1.3.4 SenseAmplifiers................................................ 9
1.3.5 WriteDrivers.................................................... 11
1.4 SRAMDesignIssuesandChallenges.................................. 13
1.4.1 ConflictingDeviceSizeRequirements ........................ 14
1.4.2 ProcessVariation................................................ 16
1.4.3 BitlineLeakageCurrent........................................ 16
1.4.4 PartialWriteDisturbance....................................... 17
1.4.5 SoftErrors....................................................... 19
1.5 SRAMBitcellTopologies .............................................. 20
1.5.1 Non-isolatedRead-PortSRAMBitcellTopologies........... 21
1.5.2 IsolatedRead-PortSRAMBitcellTopologies................. 24
1.5.3 Low-LeakageAsymmetricSRAMBitcell .................... 27
1.6 Summary ................................................................ 29
2 DesignMetricsofSRAMBitcell............................................ 31
2.1 Standard6TSRAMBitcell:AnOverview............................. 31
2.1.1 ReadOperation ................................................. 31
2.1.2 ReadSNMMeasurement....................................... 33
2.1.3 WriteOperation................................................. 36
2.1.4 WriteSNMMeasurement...................................... 37
2.1.5 RelationshipsBetweenTransistorDriveStrengths ........... 38
2.2 OtherSRAMBitcellStabilityMetrics................................. 39
2.2.1 N-CurveStabilityMetrics...................................... 39
2.2.2 StaticVoltageandCurrentMetrics ............................ 42
ix
x Contents
2.2.3 PowerMetrics................................................... 43
2.2.4 DependenciesofSPNMandWTP............................. 43
2.2.5 DependenceontheBitcellRatio............................... 44
2.2.6 DependenceontheSupplyVoltageV ...................... 45
DD
2.3 BitlineMeasurementDesignMetrics.................................. 45
2.3.1 ReadStabilityMeasurement ................................... 46
2.3.2 WriteabilityMeasurement...................................... 49
2.4 DynamicStabilityAnalysis ............................................ 51
2.4.1 DynamicReadStability ........................................ 52
2.4.2 DynamicWriteStability........................................ 54
2.5 Summary ................................................................ 56
3 Single-EndedSRAMBitcellDesign........................................ 57
3.1 Introduction ............................................................. 57
3.2 SRAMBitcellTopologies .............................................. 59
3.2.1 TransmissionGateBasedAccess6T(TG-6T)SRAMBitcell 59
3.2.2 SeparateRead-Port8TSRAMBitcell......................... 61
3.3 Single-Ended6TSRAM(SE-SRAM)Bitcell......................... 62
3.3.1 ArrayOrganizationofSE6TSRAMBitcell.................. 64
3.3.2 ReadOperation ................................................. 65
3.3.3 WriteOperation................................................. 66
3.4 ReadStabilityandWriteAbilityMargins ............................. 67
3.4.1 ReadStabilityMargin(SNM).................................. 67
3.4.2 Write-AbilityMargin(WAM).................................. 68
3.5 SizingofReadandWriteAssistTransistorsinSE6TBitcell........ 71
3.5.1 SizingofReadAssistTransistor............................... 72
3.5.2 SizingofWriteAssistTransistor .............................. 76
3.5.3 FloorPlantoEliminatethePWD.............................. 76
3.6 PerformanceandPowerDissipation ................................... 78
3.6.1 ReadAccessTimeDistribution................................ 79
3.6.2 PowerandLeakageDissipation................................ 80
3.7 Summary ................................................................ 82
4 2-PortSRAMBitcellDesign................................................ 83
4.1 Introduction ............................................................. 83
4.2 Existing2-PortSRAMBitcells......................................... 85
4.2.1 Standard8TSRAMBitcell..................................... 85
4.2.2 DifferentialBiasing7TSRAMBitcell ........................ 86
4.3 2-Port6TSRAMBitcell................................................ 88
4.3.1 ArrayOrganization............................................. 89
4.3.2 ReadandWriteOperationsin2-Port6TBitcell .............. 90
4.4 ReconfiguredRead-Portofa2-Port6TBitcell........................ 91
4.4.1 RBLLeakageandGateTunnellingCurrents.................. 94
4.4.2 ReadBitlineLeakageScenario-1.............................. 95
4.4.3 ReadBitlineLeakageScenario-2.............................. 96
