RISC System/6000 PowerPC System Architecture

347 Pages·1994·160.754 MB·English

by  International Business Machines Inc.

INTERNATIONAL BUSINESS MACHINES, INC.

RISC System/6000
PowerPC" Architecture
System
First Edition (July 1994)
This edition notice applies to the RISC System/6000 PowerPC System Architecture
Manual.
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RISC /6000
System
PowerPC" System Architecture
Edited by Frank Levine & Steve Thurber
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ISBN 1-55860-344-1
Table of Contents
List Of Figures .......ccceeeeeieneeceieeennnceennaacnnns xiii
ListofTables ......ccceeeeeeescns Cheeses eeseeaeaeaaeeeas XV
Preface....... essences Ceeeees te secceessseceseseicsssieas axix
Chapter 1 Introduction
1.1 Memory Architecture ............ccoiuiiiiiiiiiii
1.2 Definition of TEMS ....vvviiiiirannrensnrannssanaaranasssssssssnsssnnnns
1.2.1 RESEIrved .......ouveeencennnrsannssassssnsnssnaassnssssasnssnsnsnns WWOWNMDND=
iis
1.2.2 Reserved/Unimplemented ..............oiiiiiiiiiiiiiiiiiiiiaeiiasas
1.2.3 Addressing Notation ............coiiiiiiiiiiiiiiiiiiii
1.2.4 Symbolic Notation .........c.coeieiiiiiiiiiiiiii
HA
1.3 Reliability, Availability, and Serviceability (RAS) ...................onnen
Chapter 2 PowerPC Processor Architecture
2.1 PowerPC Implementation Specific User's Manual ........................
2.1.1 Processor Requirements ...........cciviiiiiiiiiiiiiiiiiiiaianans »
2.1.2 Hardware I/O Design Instruction Support Requirements .............
cco
rina
Chapter 3 Architected System Memory Map
3.1 MemoryMap Layout .........cuuiuuirnniiniinnirin 7
3.2 Architected System Registers ........... 10
3.2.1 Physical Identifier Initialization (PIDI) Register ...................... 10
1
3.2.2 Connectivity Configuration Register ..................ooviiiennnn
3.2.3 Connectivity Reset Register ...............c.coiiiiiiiiiiiiiiiine 12
3.24 TimeofDayRegisters .........ccoiiuiiiiiiiiniiiiiiiiiiainenes 12
3.2.5 System Reset CountRegister ...............ooiiiiiiiiiiininnenn 12
3.2.6 Power/Keylock Status Register (PKSR) ................coiviiennn 12
Vi Table of Contents
3.2.7 Software Power On Reset Control Register .................cvvuvunn. 14
3.2.8 Software Power Off Control Register ..............oovvievvnrvnnenn. 14
3.2.9 System Specific System Registers ............covvirrinirnnrnnnnnn. 14
3.3 Architected System Interrupt Registers ..............covirvinrnnrrnnenns 14
3.3.1 Data Storage Interrupt Error Register (DSIER) ............cc.ovuu.... 14
3.3.2 SMP Early Power Off Warning (EPOW) ExternalInterrupt Vector
Register (XIVR) .......ciiiiiiiii ities ieee eee eee ean ennns 16
3.3.3 IPLCB/Global Queue Interrupt Routing Mask Location Interface ...... 16
Chapter 4 Bring-Up and Configuration Architecture
4.1 Device Configuration Architecture ..............ccoiviiiiinrrinennnrnnnns 20
4.1.1 Hardware Architecture Assumptions and Requirements ............. 21
4.2 Configuration Registers ..............c.oiiuiiiiiiininrerinrerranennnn, 22
4.2.1 Configuration SeqUeNCe ...........ciiiiiiiiiiii iene innennnnns 22
4.2.2 Architected Configuration Registers ................cvvvvevevnnnnn. 24
4.2.3 Architected Configuration Register Address Map ................... 24
4.2.4 Device Specific Configuration Registers ................cccuevun... 29
4.3 Feature ROM Scan (FRS) Architecture ..............ccovviirvnnennnrnnnns 29
4.3.1 Address Range ............ccciueiiiineiiinnrennnernnneeanneeennes 29
4.3.2 Criteriafor Required ROM ...........c.cciiiiiiiierrnrinnerennerns 30
4.3.3 ROM Type Attributes ............ccoiiiiiiiiiiii ii ineennennnnns 30
Chapter 5 NVRAM Contents and Mapping
5.1 NVRAMUSAQGE ....oiitiiit reine eiiatenneesnnnesannerannerenneeanns 35
5.1.1 ROM Specific Areas and Their Management ........................ 37
5.1.2 OCS/SP Implementations ...........c.ouiiiiiirinnernrreneennennnnns 48
5.1.3 Non-OCS Implementations ..........coviiieeiinnerennrrnnnrernnnes 53
Chapter 6 Bus Unit Controller (BUC) Architecture
6.1 BUC Addressing .........ccooviiiiiiiiininniinnrrineannraneennennenn 60
6.1.1 Addressing with T=0 (Memory Mapped or Ordinary Segments) ....... 61
6.1.2 Addressing with T=1 (Direct-Store Segments) ....................... 62
6.1.3 Load and Store AddressingModel ...............ccviviirrinnnnnnnn. 65
6.1.4 BUC Translation Control Entry (TCE) ..........vviviirrinernnrnnnnns 68
6.1.5 BUC TCE Address Register ............c.oviiiinrnrrnrenrnnenrennnn. 69
6.2 BUC Interrupt Structure ............oviniiiii ieee eee eenennens 71
6.2.1 BUC Interrupt Scenario ...........c.ovvuiiiinrinrnreeenenrnrrnnnn, 72
6.2.2 External Interrupt Vector Register (XIVR) ...........cvvvvirvnvnnnn.. 72
6.2.3 End Of Interrupt (EOI) Command ............ccvuvimenrenrnnrnrrnens. 73
Table of Contents vii
iis
6.3 BUC Data Consistency and Ordering Requirements ..................... 73
iii
Chapter 7 I0CC Architecture
7.1 System Structure .......cnrnrninii 75
74.1 Virtual Memory ......oiiiieninnn saan ann nsans 77
79
7.1.2 System Memory .....cuvuunnrnrnritaanattisaeanaasasanacasansnsass
7.1.3 Bus Memory and Bus I/O Address Space ..............cocvunnnnnnnns 79
714.4 JOCC Facilities ....ovvvrremeninrrerensssnsssnnnsnnsssennnassnnssnns 81
7.2 Bit and Byte Numbering Conventions .............coviiiiiininiennens 82
7.2.1 Big-Endian and Little-Endian Mode Concurrency .................... 82
7.2.2 Two Processor Implementations of Little-Endian Mode .............. 82
7.2.3 1/0 Load and Store Access from the Processor to the li/O ..i.....i..... 82
7.2.4 DMA Data Interchange Between I/O and Memory .................... 88
7.3 Micro Channel Bus Protocols ...........cciiiiiiiininiiiiinrrannssannnss 94
7.3.1 Micro Channel Arbitration ............coiiiiiiiiiii iicinie 94
7.3.2 BasicTransferCycle ........ccoiiiiiiiiiiiiiiiiiiii 97
7.3.3 MicroChannel BUSEITOrS ........cciiuiiinnrrnnnnnnnnsnnsnnnnnnnsns 100
7.3.4 Exception Reportingand Handling ................covviiinnans 102
7.3.5 Micro Channelinterrupts ...........ccoiiiiiii 103
7.4 10CC Programming Model ...........coiiiiiiiiiiiiiiiiiiia 104
7.41 Load and StorelInstructions .............ciiiiiiiiiiiiiiiiianaaanas 104
115
7.4.2 BUSMASIEr ...ovvviiiireenrrasnreansssasssaassssanssnnsnssnnnsnnns
7.4.3 DMA SIAVE ...ovitittrrreerrrrrrrstasssssssrsssssssannsasssnnnnnns 119
74.4 10CCCOMMANAS .....vvcnnnnrrrennnsnsssnnnnnssnnssssnansnnsssnnns 128
7.45 IOCCReQISIErS ......ccivvururnrnrnnsarucnrititiaiasasnsnnanannnns 130
7.46 10CCInterruptStructure .........ccvvimiiniiiiinriitiiarnanannanns 137
7.4.7 Non-Recoverable Errors .........ccoiiiiiiiiinnnreannrnassssannsnnns 141
7.48 Recoverable Errors .........ceuieeusirsnsnreannrsasnrsassssasnsnnnns 143
ries
Chapter 8 System Resources
8.1 OperatorInterface .............cveieirimimiiiin ee 153
8.1.1 Display Interface ...........coiuiuiiiiiiiiiiiiiii 153
iain
8.1.2 IPL/Operation Mode ..........ccuvurenrnrieiiinnnnnntnirnenseasiannans 154
8.1.3 Operator Reset ............cccieirimiiiiiiii 155
8.2 Non-Volatile Random Access Memory (NVRAM) ..i......i....ccioieinnnnnn. 156
156
8.3 Timer Facilities ....ovvvvrrnnnnerrnrnannarssssansseransnannannsannennens
156
8.3.1 Timeof Day ClOCK ......ccvuriernrnnriiiiii
8.3.2 TimeBaseEnable ........ciineiiiiiiiiii 156
8.3.3 Symmetric Multi-Processor (SMP) Synchronization .................. 156
viii
Table of Contents
Chapter 9 External Interrupt Architecture
9.1 External Interrupt Overview .............c.oiiiiiiinreinein nn innnrnnens 157
9.1.1 System Level Interrupt Register Overview ..................cvuvu... 159
9.1.2 Interrupt Routing Layer ............c.oouiiiiiiiiii ieee enennenns 162
9.1.3 Interrupt Presentation Layer ..............c.ooviiiiierinennnrnnnnns. 163
9.2 Interrupt Register Definition Details ................ccovivvivnnnvnnnnn, 165
9.2.1 External Interrupt Request Register (XIRR) ............ccovvvennnnn. 165
9.2.2 Current Processor Priority Register (CPPR) ...........ccoovevvnenn.. 167
9.2.3 External Interrupt Source Register (XISR) ..........vovvievenrennenns 167
9.2.4 Queued Interrupt Request Register (QIRR) ............ccvvvvnennnn.. 169
9.2.5 Most Favored Request Register (MFRR) ..............cccvivvnvnnnn.. 169
9.2.6 Global Queue Interrupt Request Register (G_LQIRR) ................. 170
9.2.7 SMP Global Queue Interrupt Routing Masks (GQ_IRMS) ............. 171
9.2.8 Available Processor Mask (APM) ..........c.ooviieennrrnnennnennnnns 171
Chapter 10 System Exception Processing
iii
10.1 Exception Handling ............ociiiiiiiiiiii ie ieee eaeenennns 173
10.1.1 Target Market Categories ...........cvviiiinrinernennernnrnnnennsn 174
10.1.2 Interrupts and Checkstop .........c.covviiiiiriie ieee ee nnennns 174
10.1.3 Exception Conditions ............cciiiiiiiiiiiiii ieee ennernnns 175
10.1.4 Processor Designs ........ccuuiiiiine ii iiirinesarrineennranennn,s 178
10.1.5 BUC DeSIgNS ....uuiiiiiii ieee titties ieee saneaneennennns 179
10.1.6 Real Address M«emotryiMtaipped I/O ...........covviivinernnrnnnennen 179
10.1.7 MUIPrOCESS.Orcutieteeta eaetetrtanene sreemsaeananerannneenns 179
10.1.8 Diagnostics ite teat aan 180
10.1.9 System Exception Support Facilities ..............c.coovveevvnrnnn.. 180
10.1.10System Exception IPLCB Interface ..............ccvuvvenrnnrvnnennn. 180
Chapter 11 System Bus Architecture
11.1 BOX BUS OVEIVIEW Leet tii ti eee ease eee seen e arenes 183
e
11.1.1 60X Bus Memory Coherence ..........uuvueinreneeneneenennrnnenens 184
11.1.2 60X Bus Transfer Protocols ............ooieieineneneerennnrnrnnnnns 184
11.2 6XX System Bus OVerVIEW .........vueiiieiiinreeer a eeeereearananenn, 185
Chapter 12 Bring-Up Function and IPLCB
ieee eee
12.1 SMP Bring-Up FUNCtion ...........cciiiiiiiii ieee 187
12.2 IPL Control Block (IPLCB) Interface ............vuveeeeeernenennnnnnnnn. 188
12.2.1 Purpose of the IPLCB ...........cciuinineeeen 188