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About Reviews: Nanoelectronics Era: Novel Device Technologies Enabling Systems On Chips
The document discusses challenges in continuing to scale down CMOS transistors according to Moore's Law. Novel device technologies like high-k dielectrics, strained silicon channels, SOI, and multi-gate transistors can help scale CMOS to 5nm gate lengths. However, power dissipation and variability issues will limit complex chip design. The document also briefly outlines non-CMOS memory and logic devices and opportunities for hybrid systems-on-chips combining different components and functions on a single microchip.
Detailed Information
| Author: | ['Rajdeep Banerjee'] |
|---|---|
| Publication Year: | 2012 |
| Pages: | 14 |
| Language: | English |
| Format: | |
| Price: | FREE |
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