Table Of ContentRELIABILITY, YIELD, AND
STRESS BURN-IN
A Unified Approach for Microelectronics Systems
Manufacturing & Software Development
RELIABILITY, YIELD, AND
STRESS BURN-IN
A U nified Approach for Microelectronics
Systems Manufacturing & Software
Development
by
Way Kuo, Wei-Ting Kary Chien, Taeho Kim
r....
"
SPRINGER SCIENCE+BUSINESS MED~ LLC
Library of Congress Cataloging-in-Publication Data
Kuo, Way, 1951-
Reliability, yield, and stress bum-in : a unified approach for
microelectronics systems manufacturing & software development I by
Way Kuo, Wei-Ting Kary Chien, Taeho Kim.
p. em.
Includes bibliographical references and index.
ISBN 978-0-7923-8107-5 ISBN 978-1-4615-5671-8 (eBook)
DOI 10.1007/978-1-4615-5671-8
I. Integrated circuits--Design and construction--Reliability.
2. Microelectronics--Reliability. 3. Computer software
-Development--Reliability. 4. Semiconductors--Computer programs-
-Reliability. I. Chien, Wei-Ting Kary, 1965- II. Kim, Taeho, 1960-
III. Title.
TK7874.K867 1998
621.381--dc21 97-39195
CIP
Copyright © 1998 by Springer Science+B usiness Media New York
Originally published by Kluwer Academic Publishers in 1998
Softcover reprint of the hardcover 1st edition 1998
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo
copying, recording, or otherwise, without the prior written permission of the
publisher, Springer Science+Business Media, LLC.
Printed on acid-free paper.
v
To our wives
Chaochou Lee, Ching-Jung Lin, Dongyeon Shin
CONTENTS
Preface xix
Acknowledgements xxv
1 Overview of Design, Manufacture, and Reliability 1
1.1 Production and Manufacturing Issues 1
1.1.1 Concurrent Engineering . . . 2
1.1.2 Agile Manufacturing Systems . 3
1.1.3 System Design . . . . . . . . . 4
1.2 Taguchi Method in Quality Engineering 5
1.2.1 Minimizing Variability . . . . . . 6
1.2.2 On-line and Off-line Quality Control 7
1.2.3 Design Sequence . . . . . . . . 7
1.2.4 Experimental Design. . . . . . 7
1.3 Manufacturing Design and Reliability 9
1.3.1 Life-Cycle Approach 9
1.3.2 CAD/CAM Systems 11
1.3.3 Mechanical Design 11
1.3.4 Electrical Design . . 13
1.3.5 Integrated Design. . 13
1.3.6 Intelligent Manufacturing 15
1.3.7 Component and System Failure Modes. 16
1.3.8 Probabilistic Design 16
1.3.9 Software Design 16
1.4 Reliability Standards. 17
1.4.1 Hardware. 17
1.4.2 Software.. 21
1.4.3 Reminders. 21
1.5 Conclusions.... 23
2 Integrating Reliability into Microelectronics Manufacturing 25
2.1 Microelectronics Manufacturing . 25
2.1.1 Technology Trend .... 25
2.1.2 Semiconductor Devices. . 26
2.1.3 Manufacturing Processes. 28
2.2 New Techniques for Reliability Improvement. 37
2.2.1 BIR Approach . . . . . . . . . . 38
vii
viii
2.2.2 WLR Approach. . . . . . . . 39
2.2.3 QML Approach. . . . . . . . 41
2.3 Manufacturing Yield and Reliability 42
2.4 Conclusions ............. . 44
3 Basic Reliability Concept 45
3.1 Elements of Reliability. 46
3.1.1 Failure Rate. . . 46
3.1.2 Hazard Rate .. 46
3.1.3 Hazard Rate Family 48
3.1.4 Mean Time to Failure 50
3.1.5 Mean Residual Life. . 51
3.1.6 Behavior of Failures 52
3.2 Some Useful Life Distributions 55
3.2.1 Exponential Distribution 56
3.2.2 Normal Distribution . . 56
3.2.3 Lognormal Distribution 57
3.2.4 Gamma Distribution. 58
3.2.5 Weibull Distribution . 58
3.3 Strength and Stress Analysis 59
3.4 Multicomponents Systems 61
3.4.1 Series System . . . 61
3.4.2 Parallel System . . 61
3.4.3 k-out-of-n Systems 62
3.4.4 Non-series-parallel Systems 63
3.5 Conclusions........ 64
4 Yield and Modeling Yield 65
4.1 Definitions and Concept 65
4.1.1 Overall Yield . . . 65
4.1.2 Defects ...... 67
4.1.3 Critical Area and Defect Density 67
4.1.4 Defect Size Distribution 68
4.2 Yield Models . . . . . . . . . 73
4.2.1 Poisson Yield Model . 73
4.2.2 Murphy's Yield Model 75
4.2.3 Seed's Yield Model . . 75
4.2.4 Negative Binomial Yield Model 75
4.2.5 Other Yield Models ..... . 76
4.2.6 Different Approaches to Yield Modeling 77
4.3 Yield Prediction ..... 80
4.3.1 Scale Factors . . . 80
4.3.2 Prediction Models 80
4.4 Yield Estimation . . . . . 81
4.4.1 Test Chips and Structures. 82
4.4.2 Yield Estimation from Test Chips Measurements 82
4.4.3 Monte-Carlo Simulation . . . . . . . . . . . . . . 83
ix
4.5 Fault Coverage and Occurrence . 84
4.6 Yield-reliability Relation Model . 85
4.7 Cost Model 90
4.8 Conclusions . . . . . . 91
5 Reliability Stress Tests 93
5.1 Accelerated Life Tests ....... . 93
5.1.1 Time Transformation Models 95
5.1.2 The Arrhenius Equation ... 97
5.1.3 The Eyring Reaction Rate Model. .102
5.1.4 Mountsinger's Law . . . . . . . . 102
5.1.5 The Power Law. . . . . . . . . . 102
5.2 Environmental Stress Screening (ESS) . 103
5.2.1 Characteristics of ESS . 103
5.2.2 Optimization of ESS . . 103
5.2.3 Accelerating Stresses . . 105
5.2.4 Screening Tests. . . . . 109
5.3 Failures and Reliability Prediction . 113
5.3.1 Failures in Semiconductor Devices . 113
5.3.2 Reliability Modeling . . . . . . . . . 116
5.3.3 Strength-Stress Model . . . . . . . . 117
5.3.4 Reliability Models in MIL-HDBK-217 . 117
5.3.5 Reliability Model of British Telecommunications (BT) . 120
5.4 Conclusions........................ . 123
6 Burn-in Performance, Cost, and Statistical Analysis 125
6.1 Design of Burn-in. . . . . . . . . . 125
6.1.1 Purpose and Definition . . 125
6.1.2 Mixture of Distributions. . 126
6.1.3 Levels of Burn-in. . . . . . 129
6.1.4 Burn-in Procedures. . . . . 132
6.1.5 Incompatibility and Compatibility Factors. . 147
6.2 Performance and Cost Modeling . 149
6.2.1 Performance Criteria. . . . . . . . 149
6.2.2 Cost Functions . . . . . . . . . . . 150
6.2.3 Burn-in Cost Function Overview . 152
6.3 Burn-in Optimization .......... . 157
6.4 Statistical Approaches for Burn-in Analysis . 159
6.4.1 The Maximum Likelihood Estimation Technique . 160
6.4.2 Likelihood Ratio Test . . . . 165
6.4.3 Total Time on Test (TTT) . 166
6.4.4 Probability Plots . . . 169
6.4.5 Bayesian Approach . . 170
6.5 Conclusions......... . 175
x
7 N onparametric Reliability Analysis 177
7.1 The Proportional Hazard Rate Model . 178
7.2 The Life Table Estimator (LTE) ... . 180
7.3 The Kaplan-Meier Product Limits Estimator . 180
7.3.1 Re-distribution Methods. . 184
7.3.2 A Misconception . . . . . . . . . . . . . 186
7.3.3 Left-censored Data. . . . . . . . . . . . 187
7.3.4 Handling Both Left- and Right-censored Data. . 188
7.3.5 The Revised KME Method . . . . . . . . 190
7.3.6 The Nonparametric Bayesian Approach . 201
7.4 Goodness-of-fit (GOF) Tests. . . . . . . . 202
7.4.1 Testing V-shaped Hazard Rates. . 204
7.4.2 Testing Exponentiality. . . 205
7.4.3 Cumulative Hazard Plots . 206
7.4.4 Testing GOF . . 210
7.5 Smoothing Techniques . 211
7.6 Conclusions . . . . . . . 213
8 Parametric Approaches To Decide Optimal System Burn-in
Time 215
8.1 A Time-independent Model . . . . . . . . . . . . . . . 216
8.1.1 Stress Curves . . . . . . . . . . . . . . . . . . . 216
8.1.2 System and Subsystem Burn-in Temperature . 219
8.1.3 Compatibility Factors . 221
8.1.4 Cost Consideration . . 222
8.1.5 Evaluation ...... . 224
8.2 A Time-dependent Model . . . 227
8.2.1 Field and Shop Repair Costs . 228
8.2.2 Time-dependent Compatibility Factors . . 229
8.2.3 The Nonlinear Mixed-integer Optimization Model . 231
8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9 Nonparametric Approach and Its Applications to Burn-in 243
9.1 Introduction........... . 243
9.2 Methods............. . 247
9.2.1 Testing Exponentiality . . 247
9.2.2 The PAY Algorithm . . . 249
9.3 Applications........... . 250
9.3.1 Total Cost and Warranty Plan . 250
9.3.2 Optimal Burn-in Time . . 251
9.4 Conclusions . . . . . . . . . . . . . . . . 258
10 Nonparametric Bayesian Approach for Optimal Burn-in 261
10.1 The Dirichlet Distribution. . . . 262
10.2 The Model Formulation . . . . . 265
10.2.1 Adding Extra Samples . . 267
10.2.2 Setting o:s . . . . . . . . . 267
xi
10.2.3 The Posterior Hazard Rate . 268
10.2.4 When SiS Are Large . 269
10.2.5 Setting f3 . . . . . . . . . . . 270
10.3 Other Considerations. . . . . . . . . 271
10.3.1 Determining the Optimal System Burn-in Time. . 271
10.3.2 Determining Sample Size . 273
10.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . 279
11 The Dirichlet Process for Reliability Analysis 281
11.1 Method . . . . . . . . . . . . . . . . . . . . . 281
11.2 Variance Reduction in the Dirichlet Process . . . 283
11.2.1 An Alternative Approach . . . . . . . . . 293
11.3 Determining Optimal Burn-in Time Using the Dirichlet Process. 298
11.3.1 Method . 298
11.4 Conclusions .............................. 304
12 Software Reliability and Infant Mortality Period of the Bath-
tub Curve 305
12.1 Basic Concept and Definitions. . . . . . . . . . 306
12.1.1 Failures and Faults. . . . . . . . . . . . 306
12.1.2 Environment and Operational Profile. . 306
12.1.3 Software Reliability .......... . 306
12.1.4 Characteristics of Software Reliability . 307
12.1.5 Unified Theory for Software and Hardware Reliability . 308
12.2 Stochastic Software Reliability Models . 308
12.2.1 Types of Reliability Models . . . . . 308
12.2.2 The Jelinski-Moranda Model ... . 309
12.2.3 The Schick and Wolverton Model . . 311
12.2.4 The Littlewood Model . . . . . . . . 311
12.2.5 The Weibull Order Statistics Model . 312
12.2.6 The Bayesian JM Models . . . . . . . 312
12.2.7 Empirical Bayes ........... . 313
12.2.8 Nonhomogeneous Poisson Process Models . 314
12.3 The Non-stochastic Software Reliability Models. . 316
12.3.1 The Input-domain-based Model . . 316
12.3.2 The Fault-seeding Model .... . 317
12.4 A Proposed Procedure of Testing Data. . 318
12.4.1 Completely Monotone . . . . . . . 318
12.4.2 Using GAMS to Solve the Optimization Model. . 319
12.4.3 Using Different cis ... . . 323
12.4.4 The Envelopes . . . . . . . 324
12.5 Software Reliability Management . 324
12.6 Conclusions . . . . . . . . . . . . . 327
Epilogue: Cost-effective Design for Stress Burn-in 331
References 333
