Rapid System Prototyping with FPGAs: Accelerating the design process

321 Pages·2005·5.88 MB·English

by  RC Cofer

Rapid System Prototyping
with FPGAs

Rapid System Prototyping
with FPGAs
By R.C. Cofer and
Benjamin F. Harding
AMSTERDAM • BOSTON • HEIDELBERG • LONDON
NEW YORK • OXFORD • PARIS • SAN DIEGO
SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO
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ISBN-13: 978-0-7506-7866-7
ISBN-10: 0-7506-7866-6
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Printed in the United States of America
Illustrations by Juli M. Cofer
Cover image of development board used with permission of Avnet, Inc.
Photography by RC Cofer
Dedication
To Juli, whose love, support, assistance and patience
made this book possible. I am lucky to have you as my wife.
My special thanks to God and my parents who have
encouraged and supported me throughout this project.

—RC
This dedication is to my two best friends.
To Colleen, my wife and beacon,
whose love and encouragement guides me.
To my son Bryan who brightens every day.
I love both of you endlessly.
—Ben

Contents
Chapter 1: Introduction ........................................................................................1
1.1 FPGA Rapid Design Implementation Potential .............................................2
1.2 Rapidly Evolving Technology Field .................................................................4
1.3 Design Skill Set Crossover ...............................................................................4
1.4 Hardware Knowledge for Software/Firmware Designers ..................................6
1.5 Software Knowledge for Hardware Designers ..................................................7
1.6 When FPGA Technology May Not Be an Ideal Fit ........................................8
1.7 When FPGAs Technology May Be Appropriate .............................................9
1.8 Summary .........................................................................................................11
Chapter 2: FPGA Fundamentals..........................................................................13
2.1 Overview ........................................................................................................13
2.1.1 Categories of Programmable Logic ......................................................13
2.1.2 SPLD Device Overview ......................................................................16
2.1.3 CPLD Device Overview .....................................................................17
2.1.4 FPGA Device Overview .....................................................................20
2.1.5 FPGA Types ........................................................................................22
2.2 SRAM-Based FPGA Architecture ................................................................24
2.2.1 FPGA Logic Block Structure ..............................................................25
2.2.2 FPGA Routing Matrix and Global Signals .........................................27
2.2.3 FPGA I/O Blocks.................................................................................28
2.2.4 FPGA Clock Resources ......................................................................30
2.2.5 FPGA Memory ....................................................................................32
2.3 Advanced FPGA Features .............................................................................32
2.4 Summary .........................................................................................................33
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Contents
Chapter 3: Optimizing the Development Cycle ......................................................35
3.1 Overview ........................................................................................................35
3.2 FPGA Design Flow.........................................................................................36
3.2.1 Requirements Phase ...........................................................................41
3.2.2 Architecture and Design Phase ...........................................................42
3.2.3 Implementation Phase .........................................................................46
3.2.4 Verification Phase ................................................................................48
3.3 Summary ........................................................................................................49
Chapter 4: System Engineering ............................................................................51
4.1 Overview ........................................................................................................51
4.2 Common Design Challenges and Mistakes ...................................................52
4.3 Defined FPGA Design Process ......................................................................53
4.4 Project Engineering and Management ..........................................................55
4.4.1 Team Communication .........................................................................56
4.4.2 Design Reviews ....................................................................................57
4.4.3 Budgets and Scheduling ......................................................................59
4.5 Training ..........................................................................................................61
4.6 Support ...........................................................................................................63
4.7 Design Configuration Management ...............................................................64
4.7.1 Controlling the FPGA Design in the Lab...........................................67
4.7.2 Archiving the Design .........................................................................68
4.8 Summary .........................................................................................................70
Chapter 5: FPGA Device-Level Design Decisions ...................................................71
5.1 Overview .......................................................................................................71
5.2 FPGA Selection Categories ..........................................................................72
5.2.1 FPGA Manufacturer Selection ..........................................................72
5.2.2 Family Selection .................................................................................73
5.2.3 Device Selection .................................................................................74
5.2.4 Package Selection ...............................................................................77
5.3 Design Decisions ...........................................................................................78
5.3.1 Data Flow through the FPGA ............................................................78
5.3.2 Informed I/O Pin Assignments ...........................................................79
5.4 Device Selection Checklist ...........................................................................83
5.5 Summary ........................................................................................................85
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Contents
Chapter 6: Board-Level Design Decisions and Allocation ........................................87
6.1 Overview ........................................................................................................87
6.2 Packaging .......................................................................................................88
6.3 BGA Component Considerations .................................................................90
6.3.1 BGA Signal Breakout ..........................................................................90
6.3.2 Mounting and Reworking BGA Components ....................................92
6.3.3 BGA I/O to Signal Assignment ..........................................................93
6.3.4 BGA Trace Signal Access ...................................................................94
6.4 I/O Assignment Iteration ...............................................................................95
6.5 FPGA Device Schematic Symbol Generation ..............................................96
6.6 Thermal ..........................................................................................................96
6.7 Board Layout .................................................................................................97
6.7.1 Device Placement and Orientation ....................................................98
6.7.2 Headers and Internal Signal Access (Test and Configuration Cable) 98
6.8 Signal Integrity ...............................................................................................99
6.8.1 Signal Protocol Choices and Implementation ....................................99
6.9 Power ............................................................................................................100
6.9.1 Device Decoupling Considerations ...................................................100
6.10 Summary ......................................................................................................102
Chapter 7: Design Implementation .....................................................................103
7.1 Overview ......................................................................................................103
7.2 Design Architecture .....................................................................................104
7.2.1 Synchronous Design ..........................................................................105
7.2.2 Hierarchical versus Flat Design .........................................................106
7.2.3 Implementing a Hierarchical Design ................................................108
7.3 Design Entry .................................................................................................109
7.3.1 Dual Nature of HDL Languages ........................................................111
7.3.2 HDL Coding Guidance .....................................................................111
7.3.3 Tools...................................................................................................114
7.4 RTL...............................................................................................................115
7.5 Synthesis .......................................................................................................118
7.5.1 Logical Synthesis ...............................................................................118
7.5.2 Physical Synthesis ..............................................................................120
7.5.3 Preparing a Design for Synthesis .......................................................120
7.5.4 Design Inference versus Instantiation ...............................................122
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