Radio Frequency Integrated Circuit Design

534 Pages·2010·8.26 MB·English

by  John W. M. Rogers

Radio Frequency Integrated Circuit Design
Second Edition
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Radio Frequency Integrated Circuit Design
Second Edition
John W. M. Rogers
Calvin Plett
artechhouse.com
Library of Congress Cataloging-in-Publication Data
A catalog record for this book is available from the U.S. Library of Congress.
British Library Cataloguing in Publication Data
A catalogue record for this book is available from the British Library.
ISBN-13: 978-1-60783-979-8
Cover design by Igor Valdman
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10 9 8 7 6 5 4 3 2 1
Contents
Foreword to the First Edition xiii
Preface xii
Acknowledgments xix
ChaptER 1
Introduction to Communications Circuits 1
1.1 Introduction 1
1.2 Lower Frequency Analog Design and Microwave Design Versus
Radio-Frequency Integrated Circuit Design 2
1.2.1 Impedance Levels for Microwave and Low-Frequency
Analog Design 2
1.2.2 Units for Microwave and Low-Frequency Analog Design 2
1.3 Radio-Frequency Integrated Circuits Used in a
Communications Transceiver 4
1.4 Overview 5
References 6
ChaptER 2
Issues in RFIC Design: Noise, Linearity, and Signals 7
2.1 Introduction 7
2.2 Noise 7
2.2.1 Thermal Noise 8
2.2.2 Available Noise Power 8
2.2.3 Available Power from Antenna 9
2.2.4 The Concept of Noise Figure 10
2.2.5 The Noise Figure of an Amplifier Circuit 14
2.2.6 Phase Noise 16
2.3 Linearity and Distortion in RF Circuits 18
2.3.1 Power Series Expansion 19
2.3.2 Third-Order Intercept Point 22
2.3.3 Second-Order Intercept Point 24
2.3.4 The 1-dB Compression Point 25
2.3.5 Relationships Between 1-dB Compression and IP3 Points 26
2.3.6 Broadband Measures of Linearity 27
2.4 Modulated Signals 29
2.4.1 Phase Modulation 31
2.4.2 Frequency Modulation 36

i Contents
2.4.3 Minimum Shift Keying (MSK) 38
2.4.4 Quadrature Amplitude Modulation (QAM) 39
2.4.5 Orthogonal Frequency Division Multiplexing (OFDM) 40
References 40
ChaptER 3
System Level Architecture and Design Considerations 43
3.1 Transmitter and Receiver Architectures and Some Design
Considerations 43
3.1.1 Superheterodyne Transceivers 43
3.1.2 Direct Conversion Transceivers 45
3.1.3 Low IF Transceiver and Other Alternative Transceiver
Architectures 47
3.2 System Level Considerations 48
3.2.1 The Noise Figure of Components in Series 48
3.2.2 The Linearity of Components in Series 52
3.2.3 Dynamic Range 54
3.2.4 Image Signals and Image Reject Filtering 56
3.2.5 Blockers and Blocker Filtering 57
3.2.6 The Effect of Phase Noise on SNR in a Receiver 59
3.2.7 DC Offset 60
3.2.8 Second-Order Nonlinearity Issues 61
3.2.9 Receiver Automatic Gain Control Issues 62
3.2.10 EVM in Transmitters Including Phase Noise, Linearity, IQ
Mismatch, EVM with OFDM Waveforms, and Nonlinearity 63
3.2.11 ADC and DAC Specifications 66
3.3 Antennas and the Link Between a Transmitter and a Receiver 70
References 73
ChaptER 4
A Brief Review of Technology 75
4.1 Introduction 75
4.2 Bipolar Transistor Description 75
4.3 b Current Dependence 78
4.4 Small-Signal Model 78
4.5 Small-Signal Parameters 79
4.6 High-Frequency Effects 80
4.6.1 f as a Function of Current 82
T
4.7 Noise in Bipolar Transistors 83
4.7.1 Thermal Noise in Transistor Components 83
4.7.2 Shot Noise 84
4.7.3 1/f Noise 84
4.8 Base Shot Noise Discussion 85
4.9 Noise Sources in the Transistor Model 86
4.10 Bipolar Transistor Design Considerations 86
4.11 CMOS Transistors 87
Contents ii
4.11.1 NMOS Transistor Operation 89
4.11.2 PMOS Transistor Operation 90
4.11.3 CMOS Small-Signal Model 90
4.11.4 f and f for CMOS Transistors 92
T max
4.11.5 CMOS Small-Signal Model Including Noise 92
4.12 Practical Considerations in Transistor Layout 98
4.12.1 Typical Transistors 98
4.12.2 Symmetry 98
4.12.3 Matching 99
4.12.4 ESD Protection and Antenna Rules 100
References 100
ChaptER 5
Impedance Matching 101
5.1 Introduction 101
5.2 Review of the Smith Chart 103
5.3 Impedance Matching 106
5.4 Conversions Between Series and Parallel Resistor-Inductor
and Resistor-Capacitor Circuits 111
5.5 Tapped Capacitors and Inductors 112
5.6 The Concept of Mutual Inductance 114
5.7 Matching Using Transformers 116
5.8 Tuning a Transformer 117
5.9 The Bandwidth of an Impedance Transformation Network 118
5.10 Quality Factor of an LC Resonator 120
5.11 Broadband Impedance Matching 122
5.12 Transmission Lines 125
5.13 S, Y, and Z Parameters 126
References 128
ChaptER 6
The Use and Design of Passive Circuit Elements in IC Technologies 131
6.1 Introduction 131
6.2 The Technology Back End and Metalization in IC Technologies 131
6.3 Sheet Resistance and the Skin Effect 132
6.4 Parasitic Capacitance 134
6.5 Parasitic Inductance 136
6.6 Current Handling in Metal Lines 137
6.7 Poly Resistors and Diffusion Resistors 137
6.8 Metal-Insulator-Metal Capacitors and Stacked
Metal Capacitors 138
6.9 Applications of On-Chip Spiral Inductors and Transformers 139
6.10 Design of Inductors and Transformers 140
6.11 Some Basic Lumped Models for Inductors 142
6.12 Calculating the Inductance of Spirals 143
6.13 Self-Resonance of Inductors 144
iii Contents
6.14 The Quality Factor of an Inductor 144
6.15 Characterization of an Inductor 148
6.16 Some Notes about the Proper Use of Inductors 149
6.17 Layout of Spiral Inductors 152
6.18 Isolating the Inductor 153
6.19 The Use of Slotted Ground Shields and Inductors 154
6.20 Basic Transformer Layouts in IC Technologies 154
6.21 Multilevel Inductors 157
6.22 Characterizing Transformers for Use in ICs 159
6.23 On-Chip Transmission Lines 160
6.23.1 Effect of Transmission Line 161
6.23.2 Transmission Line Examples 161
6.24 High-Frequency Measurement of On-Chip Passives
and Some Common De-Embedding Techniques 164
6.25 Packaging 165
6.25.1 Other Packaging Techniques and Board
Level Technology 168
References 169
ChaptER 7
LNA Design 171
7.1 Introduction and Basic Amplifiers 171
7.1.1 Common-Emitter/Source Amplifier (Driver) 171
7.1.2 Simplified Expressions for Widely Separated Poles 175
7.1.3 The Common-Base/Gate Amplifier (Cascode) 176
7.1.4 The Common-Collector/Drain Amplifier
(Emitter/Source Follower) 178
7.2 Amplifiers with Feedback 181
7.2.1 Common-Emitter/Source with Series Feedback
(Emitter/Source Degeneration) 181
7.2.2 The Common-Emitter/Source with Shunt Feedback 183
7.3 Noise in Amplifiers 186
7.3.1 Input Referred Noise Model of the Bipolar Transistor 186
7.3.2 Noise Figure of the Common-Emitter Amplifier 188
7.3.3 Noise Model of the CMOS Transistor 190
7.3.4 Input Matching of LNAs for Low Noise 191
7.3.5 Relationship Between Noise Figure and Bias Current 201
7.3.6 Effect of the Cascode on Noise Figure 203
7.3.7 Noise in the Common-Collector/Drain Amplifier 204
7.4 Linearity in Amplifiers 205
7.4.1 Exponential Nonlinearity in the Bipolar Transistor 205
7.4.2 Nonlinearity in the CMOS Transistor 211
7.4.3 Nonlinearity in the Output Impedance of the
Bipolar Transistor 211
7.4.4 High-Frequency Nonlinearity in the Bipolar Transistor 213
7.4.5 Linearity in Common-Collector/Drain Configuration 213
Contents ix
7.5 Stability 214
7.6 Differential Amplifiers 215
7.6.1 Bipolar Differential Pair 215
7.6.2 Linearity in Bipolar Differential Pairs 217
7.6.3 CMOS Differential Pair 218
7.6.4 Linearity of the CMOS Differential Pair 219
7.7 Low Voltage Topologies for LNAs and the Use of
On-Chip Transformers 220
7.8 DC Bias Networks 222
7.8.1 Temperature Effects 223
7.8.2 Temperature Independent Reference Generators 224
7.8.3 Constant G Biasing for CMOS 227
M
7.9 Broadband LNA Design Example 228
7.10 Distributed Amplifiers 231
7.10.1 Trasmission Lines 233
7.10.2 Steps in Designing the Distributed Amplifier 235
References 236
Selected Bibliography 237
ChaptER 8
Mixers 239
8.1 Introduction 239
8.2 Mixing with Nonlinearity 239
8.3 Basic Mixer Operation 239
8.4 Transconductance-Controlled Mixer 240
8.5 Double-Balanced Mixer 242
8.6 Mixer with Switching of Upper Quad 245
8.6.1 Why LO Switching? 246
8.6.2 Picking the LO Level 246
8.6.3 Analysis of Switching Modulator 248
8.7 Mixer Noise 250
8.7.1 Summary of Bipolar Mixer Noise Components 256
8.7.2 Summary of CMOS Mixer Noise Components 258
8.8 Linearity 259
8.8.1 Desired Nonlinearity 259
8.8.2 Undesired Nonlinearity 259
8.9 Improving Isolation 262
8.10 General Design Comments 262
8.10.1 Sizing Transistors 263
8.10.2 Increasing Gain 263
8.10.3 Improvement of IP3 263
8.10.4 Improving Noise Figure 264
8.10.5 Effect of Bond Pads and the Package 264
8.10.6 Matching, Bias Resistors, Gain 265
8.11 Image-Reject and Single-Sideband Mixer 269
8.11.1 Alternative Single-Sideband Mixers 270