QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS (Rev. B)

80 Pages·2015·3.29 MB·English

ADS6445, ADS6444
ADS6443, ADS6442
www.ti.com SLAS531B–MAY2007–REVISEDDECEMBER2009
QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
CheckforSamples:ADS6445,ADS6444,ADS6443,ADS6442
FEATURES • PinCompatible12-BitFamily(ADS642X -
1
• MaximumSampleRate:125MSPS SLAS532A)
• 14-BitResolutionwithNoMissingCodes • FeatureCompatibleDual ChannelFamily
(ADS624X-SLAS542A,ADS644X-SLAS543A)
• SimultaneousSampleand Hold
• 3.5dB CoarseGainandupto6dB
APPLICATIONS
ProgrammableFineGainfor SFDR/SNR
• Base-StationIFReceivers
Trade-Off
• DiversityReceivers
• SerializedLVDS OutputswithProgrammable
• Medical Imaging
InternalTerminationOption
• TestEquipment
• SupportsSine,LVCMOS,LVPECL,LVDSClock
InputsandAmplitudedownto400mV
PP Table1.ADS64XXQuadChannelFamily
• InternalReferencewithExternalReference
125MSPS 105MSPS 80MSPS 65MSPS
Support
ADS644X
• NoExternalDecouplingRequiredfor 14Bit ADS6445 ADS6444 ADS6443 ADS6442
References
ADS642X
ADS6425 ADS6424 ADS6423 ADS6422
• 3.3-VAnalogand DigitalSupply 12Bit
• 64QFNPackage(9mm× 9mm)
Table2.PerformanceSummary
ADS6445 ADS6444 ADS6443 ADS6442
Fin=10MHz(0dBgain) 87 91 92 93
SFDR,dBc
Fin=170MHz(3.5dBgain) 79 83 84 84
Fin=10MHz(0dBgain) 73.4 73.4 74.2 74.3
SINAD,dBFS
Fin=170MHz(3.5dBgain) 68.3 69.3 69.4 70
Power,perchannel,mW 420 340 300 265
DESCRIPTION
The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65
MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in
a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device
includes3.5dBcoarsegainoptionthatcanbeusedtoimproveSFDRperformancewithlittledegradationinSNR.
Inadditiontothecoarsegain,finegainoptionsalsoexist,programmablein1dBstepsupto6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and
bitclocksarealsotransmittedasLVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and
internal termination options. These can be used to widen eye-openings and improve signal integrity, easing
capturebythereceiver.
TheADCchanneloutputscanbetransmittedeitherasMSBorLSBfirst and2scomplementorstraightbinary.
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2009,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B–MAY2007–REVISEDDECEMBER2009 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
DESCRIPTION (CONTINUED)
The ADS644X has internal references, but can also support an external reference mode. The device is specified
overtheindustrialtemperaturerange(–40°Cto85°C).
DD DD
AVDAGN CAP LVDLGN
BITClock DCLKP
DCLKM
CLKP PLL
CLKM
FRAMEClock FCLKP
FCLKM
DA0_P
INA_P Digital DA0_M
14-Bit Encoder
SHA ADC and DA1_P
INA_M Serializer
DA1_M
DB0_P
INB_P Digital DB0_M
14-Bit Encoder
SHA ADC and
DB1_P
INB_M Serializer
DB1_M
DC0_P
INC_P Digital DC0_M
14-Bit Encoder
SHA ADC and DC1_P
INC_M Serializer
DC1_M
DD0_P
IND_P Digital DD0_M
14-Bit Encoder
SHA ADC and DD1_P
IND_M Serializer
DD1_M
P M
F F
E E
R R
VCM Reference Parallel Serial
Interface Interface
ADS644x
DN G1 G2 G3 G4 EN TA LK ET
P CF CF CF CF S DA SC ES
S R
B0199-03
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PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED TRANSPORT
PACKAGE PACKAGE
PRODUCT PACKAGE-LEAD TEMPERATURE ORDERINGNUMBER MEDIA,
DESIGNATOR MARKING
RANGE QUANTITY
ADS6445IRGCT 250,Tape/reel
ADS6445 QFN-64(2) RGC –40°Cto85°C AZ6445
ADS6445IRGCR 2000,Tape/reel
ADS6444IRGCT 250,Tape/reel
ADS6444 QFN-64(2) RGC –40°Cto85°C AZ6444
ADS6444IRGCR 2000,Tape/reel
ADS6443IRGCT 250,Tape/reel
ADS6443 QFN-64(2) RGC –40°Cto85°C AZ6443
ADS6443IRGCR 2000,Tape/reel
ADS6442IRGCT 250,Tape/reel
ADS6442 QFN-64(2) RGC –40°Cto85°C AZ6442
ADS6442IRGCR 2000,Tape/reel
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.θ =23.17°C/W(0LFMairflow),θ
JA JC
=22.1°C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3in.x3in.PCB.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
AVDD Supplyvoltagerange –0.3to3.9 V
LVDD Supplyvoltagerange –0.3to3.9 V
VoltagebetweenAGNDandDGND –0.3to0.3 V
VoltagebetweenAVDDtoLVDD –0.3to3.3 V
Voltageappliedtoexternalpin,VCM –0.3to2.0 V
Voltageappliedtoanaloginputpins –0.3Vtominimum(3.6,AVDD+0.3V) V
T Operatingfree-airtemperaturerange –40to85 °C
A
T Operatingjunctiontemperaturerange 125 °C
J
T Storagetemperaturerange –65to150 °C
stg
Leadtemperature1,6mm(1/16")fromthecasefor10seconds 220 °C
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
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RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 3.0 3.3 3.6 V
LVDD LVDSBuffersupplyvoltage 3.0 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
pp
Inputcommon-modevoltage 1.5±0.1 V
VoltageappliedonVCMinexternalreferencemode 1.45 1.50 1.55 V
CLOCKINPUT
ADS6445 5 125
ADS6444 5 105
Inputclocksamplerate,F MSPS
srated
ADS6443 5 80
ADS6442 5 65
Sinewave,ac-coupled 0.4 1.5
LVPECL,ac-coupled ±0.8
Inputclockamplitudedifferential(V –V ) V
CLKP CLKM pp
LVDS,ac-coupled ±0.35
LVCMOS,ac-coupled 3.3
InputClockdutycycle 35% 50% 65%
DIGITALOUTPUTS
Maximumexternalloadcapacitancefromeachoutputpin Withoutinternaltermination 5
C pF
LOAD toDGND Withinternaltermination 10
R Differentialloadresistance(external)betweentheLVDSoutputpairs 100 Ω
LOAD
T Operatingfree-airtemperature –40 85 °C
A
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
LVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreference
mode(unlessotherwisenoted).
ADS6445 ADS6444 ADS6443 ADS6442
PARAMETER Fs=125MSPS Fs=105MSPS Fs=80MSPS Fs=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
RESOLUTION 14 14 14 14 Bits
ANALOGINPUT
Differentialinputvoltage 2.0 2.0 2.0 2.0 VPP
range
Differentialinput 7 7 7 7 pF
capacitance
Analoginputbandwidth 500 500 500 500 MHz
Analoginputcommonmode 155 130 100 81 μA
current(perinputpinof
eachADC)
REFERENCEVOLTAGES
VREFB Internalreferencebottom 1.0 1.0 1.0 1.0 V
voltage
VREFT Internalreferencetop 2.0 2.0 2.0 2.0 V
voltage
ΔVREF Internalreferenceerror -15 ±2 15 -15 ±2 15 -15 ±2 15 -15 ±2 15 mV
(VREFT–VREFB)
VCM Commonmodeoutput 1.5 1.5 1.5 1.5 V
voltage
VCMoutputcurrent ±4 ±4 ±4 ±4 mA
capability
DCACCURACY
Nomissingcodes Assured Assured Assured Assured
EO Offseterror,acrossdevices –15 ±2 15 –15 ±2 15 –15 ±2 15 –15 ±2 15 mV
andacrosschannelswithin
adevice
Offseterrortemperature 0.05 0.05 0.05 0.05 mV/°C
coefficient,acrossdevices
andacrosschannelswithin
adevice
Therearetwosourcesof
gainerror-internal
referenceinaccuracyand
channelgainerror
EGREF Gainerrorduetointernal -0.75 0.1 0.75 -0.75 0.1 0.75 -0.75 0.1 0.75 -0.75 0.1 0.75 %FS
referenceinaccuracyalone,
(ΔVREF/2.0)%
Referencegainerror 0.0125 0.0125 0.0125 0.0125 Δ%/°C
temperaturecoefficient
EGCHAN Gainerrorofchannelalone, –1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 %FS
acrossdevicesandacross
channelswithinadevice(1)
Channelgainerror 0.005 0.005 0.005 0.005 Δ%/°C
temperaturecoefficient,
acrossdevicesandacross
channelswithinadevice
Differentialnonlinearity,Fin –0.9 ±0.6 2.0 –0.9 ±0.6 2.0 –0.9 ±0.5 1.8 –0.9 ±0.5 1.8 LSB
DNL
=50MHz
Integralnonlinearity,Fin= -5 ±3 5 -0.5 ±3 5 4.5 ±2 4.5 4.5 ±2 4.5 LSB
INL
50MHz
PSRR DCpowersupplyrejection 0.5 0.5 0.5 0.5 mV/V
ratio
POWERSUPPLY
ICC Totalsupplycurrent 502 410 360 320 mA
IAVDD Analogsupplycurrent 410 322 280 245 mA
(1) Thisisspecifiedbydesignandcharacterization;itisnottestedinproduction.
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
LVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreference
mode(unlessotherwisenoted).
ADS6445 ADS6444 ADS6443 ADS6442
PARAMETER Fs=125MSPS Fs=105MSPS Fs=80MSPS Fs=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
ILVDD LVDSsupplycurrent 92 88 80 75 mA
Totalpower 1.65 1.8 1.35 1.5 1.18 1.3 1.05 1.2 W
Powerdown(withinput 77 150 77 150 77 150 77 150 mW
clockstopped)
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
LVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreference
mode(unlessotherwisenoted).
ADS6445 ADS6444 ADS6443 ADS6442
PARAMETER TESTCONDITIONS Fs=125MSPS Fs=105MSPS Fs=80MSPS Fs=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
DYNAMICACCHARACTERISTICS
Fin=10MHz 73.7 73.8 74.4 74.5
Fin=50MHz 68.5 73.1 73.2 70 73.8 70.5 74
Fin=70MHz 72.7 69 73 73.4 73.6
Fin=100MHz 72.1 72.2 72.7 72.8
SNR
Signalto 0dBgain 69.9 70.2 70.5 70.7 dBFS
Fin=170
noiseratio MHz 3.5dB 69.4 69.7 69.7 70.2
Coarsegain
0dBgain 68.7 68.8 68.1 69.2
Fin=230
MHz 3.5dB 68.1 68.2 68.2 68.9
Coarsegain
Fin=10MHz 73.4 73.4 74.2 74.3
Fin=50MHz 68 72.3 71.7 69.5 73.5 70 73.7
Fin=70MHz 71.2 68.5 72 73 73.2
SINAD Fin=100MHz 71.8 72 72.2 72
Signalto 0dBgain 67.9 69.8 69.9 70.3 dBFS
noiseand Fin=170
distortionratio MHz 3.5dB 68.3 69.3 69.4 70
Coarsegain
0dBgain 67.8 67.7 67.6 68.3
Fin=230
MHz 3.5dB 67.9 67.6 68.1 68.4
Coarsegain
RMS Inputstiedtocommon-mode 1.05 1.05 1.05 1.05 LSB
Outputnoise
Fin=10MHz 87 91 92 93
Fin=50MHz 73 81 80 77 87 79 88
Fin=70MHz 78 74 81 86 86
SFDR Fin=100MHz 86 88 84 82
Spuriousfree 0dBgain 76 79 80 81 dBc
dynamic Fin=170
range MHz 3.5dB 79 83 84 84
Coarsegain
0dBgain 77 77 78 79
Fin=230
MHz 3.5dB 80 80 82 82
Coarsegain
Fin=10MHz 93 94 96 97
Fin=50MHz 73 87 88 77 90 79 92
Fin=70MHz 87 74 88 90 92
Fin=100MHz 89 90 87 87
HD2
Second 0dBgain 83 84 86 86 dBc
Fin=170
harmonic MHz 3.5dB 85 86 88 88
Coarsegain
0dBgain 80 81 82 83
Fin=230
MHz 3.5dB 82 83 84 85
Coarsegain
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
LVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreference
mode(unlessotherwisenoted).
ADS6445 ADS6444 ADS6443 ADS6442
PARAMETER TESTCONDITIONS Fs=125MSPS Fs=105MSPS Fs=80MSPS Fs=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin=10MHz 87 91 92 93
Fin=50MHz 73 81 80 77 87.5 79 88
Fin=70MHz 78 74 81 86 86
Fin=100MHz 86 88 84 82
HD3
Third 0dBgain 76 79 80 81 dBc
Fin=170
harmonic MHz 3.5dB 79 83 84 84
Coarsegain
0dBgain 77 77 78 79
Fin=230
MHz 3.5dB 80 80 82 82
Coarsegain
Fin=10MHz 91 91 94 95
Worst Fin=50MHz 87 87 92 93
harmonic
Fin=100MHz 90 91 92 92 dBc
(otherthan
HD2,HD3) Fin=170MHz 88 88 90 90
Fin=230MHz 87 87 87 87
Fin=10MHz 86 89.5 90 91
Fin=50MHz 71 80 75 85.5 77 85.6
THD
Total Fin=70MHz 72 79
dBc
harmonic Fin=100MHz 84.5 86 83 80.5
distortion
Fin=170MHz 73.5 77 78.5 79.5
Fin=230MHz 74 75 76 77
ENOB Fin=50MHz 11.0 11.7 11.1 11.9 11.4 12
Effective Bits
numberofbits Fin=70MHz 11.3 11.7
IMD F1=46.09MHz, 88 90 96 100
2-Tone F2=50.09MHz
dBFS
intermodulatio F1=185.09MHz, 86 88 93 96
ndistortion F2=190.09MHz
Nearchannel 90 92 94 100
Cross-talksignal
frequency=10MHz
Cross-talk dBc
Farchannel 103 105 106 108
Cross-talksignal
frequency=10MHz
Recoverytowithin1%(offinal 1 1 1 1 Clock
Inputoverload
value)for6-dBoverloadwith cycles
recovery
sinewaveinput
ACPSRR 35 35 35 35 dBc
PowerSupply <100MHzsignal,100mVPP
Rejection onAVDDsupply
Ratio
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DIGITAL CHARACTERISTICS
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1AVDD=LVDD=3.3V,I =3.5mA,R =100Ω(1).
O LOAD
AllLVDSspecificationsarecharacterized,butnottestedatproduction.
ASD6445/ADS6444
PARAMETER TESTCONDITIONS ADS6443/ADS6442 UNIT
MIN TYP MAX
DIGITALINPUTS
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 10 μA
Low-levelinputcurrent 10 μA
Inputcapacitance 4 pF
DIGITALOUTPUTS
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
Outputdifferentialvoltage|V | 250 350 450 mV
OD
OutputoffsetvoltageV Common-modevoltageofOUTPandOUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,fromeitheroutputto 2 pF
Outputcapacitance
ground
(1) I referstotheLVDSbuffercurrentsetting,R istheexternaldifferentialloadresistancebetweentheLVDSoutputpair.
O LOAD
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TIMING SPECIFICATIONS(1)
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
LVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V clockamplitude,C =5pF (2),I =3.5mA,
PP L O
R =100Ω (3),nointernaltermination,unlessotherwisenoted.
L
ADS6445 ADS6444 ADS6443 ADS6442
PARAMETER TEST Fs=125MSPS Fs=105MSPS Fs=80MSPS Fs=65MSPS UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
t Aperturejitter Uncertaintyin
J
thesampling 250 250 250 250 fsrms
instant
INTERFACE:2-wire,DDRbitclock,
14xserialization
Fromdata
Datasetup cross-overto
tsu time(4) (5) (6) bitclock 0.35 0.55 0.45 0.65 0.65 0.85 0.8 1.1 ns
cross-over
Frombitclock
Datahold cross-overto
th time(4) (5) (6) data 0.35 0.58 0.5 0.7 0.7 0.9 0.8 1.1 ns
cross-over
Fromframe
clockrising
edge
Framesetup
t cross-overto 0.35 0.55 0.45 0.65 0.65 0.85 0.8 1.1 ns
su time
bitclockrising
edge
cross-over
Frombitclock
fallingedge
Framehold cross-overto
t 0.35 0.58 0.5 0.7 0.7 0.9 0.8 1.1 ns
h time frameclock
fallingedge
cross-over
Inputclock
risingedge
Clock
t cross-overto
pd_cl propagation 3.4 4.4 5.4 3.4 4.4 5.4 3.4 4.4 5.4 3.4 4.4 5.4 ns
k delay (6) frameclock
risingedge
cross-over
Bitclock
cycle-cycle 350 350 350 350 pspp
jitter (5)
Frameclock
cycle-cycle 75 75 75 75 pspp
jitter (5)
Belowspecificationsapplyfor5MSPS≤Fs≤125MSPSand
allinterfaceoptions.
Delayfrom
inputclock
Aperture risingedgeto
t 1 2 3 1 2 3 1 2 3 1 2 3 ns
A delay theactual
sampling
instant
Aperture Channel-
delay channelwithin –250 ±80 250 –250 ±80 250 –250 ±80 250 –250 ±80 250 ps
variation samedevice
(1) Timingparametersareensuredbydesignandcharacterizationandnottestedinproduction.
(2) C istheexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) I referstotheLVDSbuffercurrentsetting;R istheexternaldifferentialloadresistancebetweentheLVDSoutputpair.
o L
(4) Timingparametersaremeasuredattheendofa2inchpcbtrace(100-Ωcharacteristicimpedance)terminatedbyR andC .
L L
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(6) RefertoOutputTimingsinapplicationsectionfortimingsatlowersamplingfrequenciesandotherinterfaceoptions.
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