Table Of ContentGustavo Neuberger · Gilson Wirth
Ricardo Reis
Protecting
Chips Against
Hold Time
Violations Due
to Variability
Protecting Chips Against Hold Time Violations
Due to Variability
Gustavo Neuberger Gilson Wirth
●
Ricardo Reis
Protecting Chips Against
Hold Time Violations Due
to Variability
Gustavo Neuberger Ricardo Reis
Instituto Federal de Educação Instituto de Informática
Ciência e Tecnologia do Rio Grande Universidade Federal do Rio Grande
do Sul(IFRS) Campus do Sul (UFRGS)
Canoas Canoas, Rio Grande do Sul, Brazil Porto Alegre, Brazil
Gilson Wirth
Depto de Eng Elétrica
Universidade Federal do Rio Grande
do Sul (UFRGS)
Porto Alegre, Brazil
ISBN 978-94-007-2426-6 ISBN 978-94-007-2427-3 (eBook)
DOI 10.1007/978-94-007-2427-3
Springer New York Dordrecht Heidelberg London
Library of Congress Control Number: 2013944679
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To my parents Lotário and Isabel, who
always gave me the support to follow my
dreams.
“Gustavo Neuberger”
To my wife Mariana, who always gave me
unconditional love and support.
“Gilson Wirth”
To my wife Lucia, to my daughter Mariana,
to my sons Guilherme and Eduardo, and to
my parents Constantino and Maria de
Lourdes.
“Ricardo Reis”
Contents
1 Introduction: Process Variations and Flip-Flops .................................. 1
2 Process Variability: Overview ................................................................. 5
2.1 Sources and Types of Variations ...................................................... 5
2.1.1 Lithography .......................................................................... 8
2.1.2 Doping ................................................................................. 8
2.2 Impact on Circuit Design ................................................................. 9
2.3 Design Techniques with Process Variations ..................................... 11
2.3.1 Monte Carlo Simulations ..................................................... 11
2.3.2 Corner Analysis ................................................................... 12
2.3.3 Statistical Static Timing Analysis (SSTA) ........................... 12
3 Flip-Flops and Hold Time Violations: Defi nitions ................................ 15
3.1 Flip-Flop Timing Metrics ................................................................. 15
3.1.1 Setup Time ........................................................................... 15
3.1.2 Hold Time ............................................................................ 16
3.1.3 Clock-to-Output Delay ........................................................ 17
3.1.4 Data-to-Output Delay .......................................................... 17
3.1.5 Delay .................................................................................... 17
3.1.6 Internal Race Immunity ....................................................... 17
3.2 Hold Time Violations ....................................................................... 18
4 Circuits Under Test: For Characterization ............................................ 21
4.1 Inverter Sensitivity ........................................................................... 21
4.2 Flip-Flop Sensitivity ........................................................................ 23
4.3 Hold Time Violation Probability ...................................................... 23
4.4 Test Circuits for Fabrication ............................................................ 25
5 Measurement Circuits: For Precise Characterization .......................... 27
5.1 Programmable Delay Line ............................................................... 27
5.2 Ring Oscillator ................................................................................. 28
vii
viii Contents
5.3 Shift Register ................................................................................... 29
5.4 Final Circuit and Layout .................................................................. 30
6 Experimental Results: Of Fabricated Circuits ...................................... 33
6.1 Measurement Flow and Setup .......................................................... 33
6.2 Ring Oscillator Frequency Variability ............................................. 35
6.3 Hold Time Violation Distribution .................................................... 37
6.4 Comparisons .................................................................................... 40
6.4.1 Different Wafers of a Same Technology .............................. 40
6.4.2 Different Technologies at Nominal Conditions ................... 41
6.4.3 Different Temperatures ........................................................ 42
6.4.4 Different Vdd’s .................................................................... 43
6.4.5 Different Technologies at Same Vdd ................................... 44
7 Systematic and Random Variability: Of Measured Results ................. 55
7.1 Separation Methods ......................................................................... 55
7.2 Separation Results ............................................................................ 56
8 Normality Tests: Of Measured Results ................................................... 69
8.1 The Tests .......................................................................................... 69
8.1.1 Wilks-Shapiro Test ............................................................... 69
8.1.2 Anderson-Darling Test ......................................................... 70
8.1.3 Kurtosis and Skewness Analysis ......................................... 71
8.2 Normality Test Results ..................................................................... 72
9 Probability of Hold Time Violations: Of Short Logic Paths ................ 77
9.1 Simulation of Dependence of Race Immunity on Vdd .................... 77
9.2 Hold Time Violation Probability Using Simulated Data ................. 80
9.3 Hold Time Violation Probability Using Measured Data .................. 84
9.3.1 Dependency on Technology ................................................. 84
9.3.2 Dependency on Flip-Flop Strength ...................................... 85
9.3.3 Dependency on Vdd. ............................................................ 86
9.3.4 Dependency on Padding ...................................................... 88
9.3.5 Dependency on Clock Skew Model .................................... 89
10 Protecting Circuits Against Hold Time Violations: Due to Process
Variability ................................................................................................. 91
10.1 Motivation ...................................................................................... 91
10.2 Protection Against Hold Time Violations ...................................... 92
10.2.1 Vdd Reduction ................................................................. 92
10.2.2 Increasing Flip-Flop Race Immunity ............................... 93
10.2.3 Padding ............................................................................ 93
Contents ix
11 Padding Effi ciency: Of the Proposed Padding Algorithm ..................... 97
11.1 Methodology .................................................................................. 97
11.2 Results ............................................................................................ 98
12 Final Remarks ......................................................................................... 103
References ........................................................................................................ 105
