Table Of Content®
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This foil set was produced by…..
Andy Miller
Senior Staff Engineer IP Solutions
Xilinx Ltd (UK)
email: [email protected]
Feedback on the use of this information and any comments for future improvements would be
gratefully received but please allow time for a reply.
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
Agenda
Q: Why use an FPGA, can’t I do it in a processor?
Q: How much work can an FPGA do?
Q: What is my design methodology?
To answer these questions, we must consider.
1) Market conditions
2) Some basic features of a Xilinx FPGA.
3) How those features are used for DSP.
4) Show me! ……. 800MHz Interpolation Filter
16 Beam Adaptive Beam Former
500 Tap Complex Filter
5) The rate of change of FPGA technology and why it is driving the market.
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
Complex Communication
Landscape
Diverse Range of Comms
Satellite
Low-tier
Technology High-tier
- Cable
Regional Area
- Satellite
- Terrestrial microwave links
- Cellular wireless
(high and low mobility)
Local Area
Wide Area
Evolving Range of
User Equipment (UE’s)
- Cell Phones
- Video Phones
Success Calls For Sophisticated Flexible Infrastructure
- PDA’s
• operate across multiple wired/wireless standards
- Portable computers
- In-car Infotainment • Adapt to new business models as they evolve.
• Implement new DSP techniques that
Sophisticated System
- increase capacity
Infrastructure must
- increase coverage
adapt to deliver
- increase QOS.
- low bit rate speech
- high bit-rate data
= Software Defined Radio
- video/image
- multimedia services
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
Software Defined Radio (SDR)
• Highly configurable hardware platform, (not so much “Software”, as “soft”.)
• Performs many sophisticated DSP tasks
• Advanced compression algorithms
• Power Control
• Channelization
• Channel Estimation/Equalization
• Forward Error Control
• Adaptive Antenna’s
• Tracking Rake Receivers for DS-SS systems
• Protocol management.
Total algorithmic complexity of the system can run into the 10’s if not 100’s of
Billions of MAC’s.
This represents a serious challenge to Systems architects responsible for
dimensioning systems that are highly flexible, but commercially viable.
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
Comparing Technologies
The question of what technology to use to realize your DSP algorithm is dependant on many
factors, not least understanding which combination of ASIC, FPGA and DSP processor
gives you the most powerful, cheapest and flexible solution to the problem. Partitioning a
DSP algorithm across these technologies requires that the capabilities of each device are
understood when striving for an optimum solution.
- ASIC’s are historically understood. There is a known design flow and many engineers.
Cheap in high volume,… always have been, always will be!
- DSP processors are well understood, powerful and flexible, many designers!
- FPGA’s, …...hmmmm……. Glue logic?
How do you measure the capability of an FPGA? (how much work per $ can it do?)
• DSP processors are not measured in gates!
• FPGA’s/ASICs are not measured in MIPs/MAC’s, they are compared against each other
using gate count because it is considered a reasonable measure of how much work they
can do.
The objective of this brief session is to leave you with a better understanding of what is
possible in Xilinx FPGA’s (Spartan-II, Virtex-E, Virtex-II), and how their capabilities can be
harnessed for high speed DSP, required for Software Defined Radio.
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
An FPGA Based SDR (Rx)
Completely flexible ‘soft’ system. Processors are still used but the high
speed parallel algorithms are implemented in re-configurable FPGA’s.
FPGA front-end signal processor:
FPGA front-end signal processor:
- Channel selection,
200Ms/s - Channel selection,
- Channel compensation
LNA = Wide BW - Channel compensation
- rate adjust,
- rate adjust,
LO Mixer Filter + F- iMlteart c+h FiltePr rogram
Mixer Filter + F i l-t eMr a+tch FiltPerro gram
DMDcihxSaenrnel Fdiletceirm +atio F d i le-t ceDirm i+gaittiaol DoPwronmg Craabomlneversion
channel decimatio d e c i-m Daitgioital Dowmna bCleonversion
chsaenlencetlion decimantio decimantio mafbillteer
Mseixleecrtion n n Progfrialtmer
AGC ADC cshealencnteioln Filtenr + Filtenr + mfaibltleer
decimate decimate
selection filter
digitally controlled
Channel control
sigma delta analogue
& digital AGC
loop.
Baseband/chip rate
Sample rate selection
processing
Filter coefficients
FPGA BaseBand Processor
FPGA BaseBand Processor
RISC/DSP Micro. - RACH detection
200ks/s - RACH detection
- Rake processor
- Rake processor
Protocol and control - (search, and track)
- (search, and track)
- FEC: Turbo Decoding, Viterbi
Applications/applets - FEC: Turbo Decoding, Viterbi
- MUD,
- MUD,
- Beam Forming.
- Beam Forming.
- Parallelism (Spatial Diversity.)
- Parallelism (Spatial Diversity.)
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
An FPGA Based SDR(Tx)
Up- Up- Filter +Filter + Filter +Filter +Programm
HPA convertconvDerDS DinDterpoliantteerpoliantterpoliantteerpolaatble filter
t S e e
Up- Up- Filter +Filter + Filter +Filter +Programm
LO M convertconvDerDS DinDterpoliantteerpoliantterpoliantteerpolaatble filter
U t S e e
S Up- Filter + Filter + Programm
convert DDS interpolate interpolate able filter
LPF DAC
Up- Filter + Filter + Programm
convert DDS interpolate interpolate able filter
Downconverter ADC
channel
control
Sample rate selection
Filter coefficients
.
RISC/DSP Micro.
- Modulator
- Modulator
Protocol and control
- FEC: Turbo enc. Conv. enc,
- FEC: Turbo enc. Conv. enc,
Applications/applets - Rate Matching
- Rate Matching
- Adaptive predistortion
- Adaptive predistortion
- beam forming
- beam forming
FPGA Configurable
Signal Processor
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
The Building Blocks of Any DSP
Algorithm from a Hardware
Perspective
Any
n Digital n+m
kHz Signal kHz
MHz MHz
Processing
Algorithm
DELAY ADDITION/SUBTRACTION
MULTIPLICATION DATA STORAGE
Any technology that can perform these functions efficiently
offers the basis of a DSP solution.
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
The limit of DSP Processors
Very Good Devices
Instruction
Program
Decode
Data • Microprocessor Architecture.
and
• Special MAC instructions.
Control
• Software, flexibility
Ext. Data
• On chip memory for program and data,
fast execution.
• Very fast clock rates (200MHz ->800MHz+).
Data RAM I/O Port
Limitations
• Fixed Architecture.
Interrupt
Multiplier
• Fixed bit sizes. Coefficient Quantisation
Stack
Signal Quantisation
ALU/ACC Status Register
.. Does this limit your choice of
algorithm?
Typical DSP Device Architecture
• SEQUENTIAL processing.
- Andy Miller ®
- General DSP - 2001
www.xilinx.com
Description:Presented by. Andy Miller Xilinx factors, not least understanding which combination of ASIC, FPGA and DSP processor . Special MAC instructions.
