Practical microcomputer programming: the 6502

489 Pages·1980·21.962 MB·English

by  Walter J. Weller

PRACTICAL
ICROCOMPUTER
PROGRAMMING:
THE 6502
W.J. WELLER
Northern Technology Books
Weller, Walter J.
Practical Microcomputer Programming: The 6502
Library of Congress Catalog Card #80-83327
International Standard Book Number: 0-930594-08-8
Copyright @ Walter J. Weller 1980
All rights reserved. No part of this publication may be
reproduced, copied or transmitted in any form or by any
mechanical or electronic means without written
permission of the copyright holder.
To the 24 years •••

TABLE OF CONTENTS
PREFACE
CHAPTER 1 STRUCTURE OF THE 6502 COMPUTER 1
Logical elements of a computer. The
function of memory. Volatility of
memory. The word and wordlength.
Address concept. RAM and ROM. The A
register. The control unit. I and P
registers. Concept of a pointer. The
computer program. Fundamental
instruction execution cycle. Classes of
computer instructions.
CHAPTER 2 THE BINARY SYSTEM AND BINARY OPERATIONS 7
Number bases. The binary system.
Logical operations. Inclusive OR. The
AND function. Masking. Complementation.
Exclusive OR. Powers of two. Binary
addition. Binary subtraction. Twos
complement arithmetic. Carry, sign and
overf low bi t s. Logical shif ts. Rotary
shif ts. Ari thmetic shif ts. Octal and
hexadec ima l.
CHAPTER 3 MACHINE AND ASSEMBLY LANGUAGES 27
Binary instructions and programming.
Mnemonic form of an instruction.
Mnemonic loader. Assembly language. The
assembly program. Definition of symbol.
Label, instruction and operand fields.
Comment field. The source program. The
assembly listing. The symbol table.
Error listing. The object program.
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CHAPTER 4 USING THE ASSEMBLY PROGRAM 36
Allocating source buffer memory. System
initialization. The A command. The L
and D commands. Writing and reading
source. Error scan func tioOo Swi tching
peripherals. Assembler error messages.
Standard I/O device assignments.
CHAPTER 5 MEMORY REFERENCING ON THE 6502 46
Addressing modes. Scratchpad memory.
General memory. Direct addressing.
Immediate mode. Indexed addressing. The
effective address. Index registers.
Indirect addressing. Pre and post
indexing.
CHAPTER 6 6502 ARITHMETIC AND LOGICAL OPERATIONS 54
Addition with and without carry.
Subtraction with and without borrow.
Minuend, subtrahend and difference. The
processor status word. Meanings of PSW
bits. Jump and branch instructions.
Condi tional branches. Branch synonyms.
Logical operations. Data types.
Looping. Block reservatioOo Half symbol
constants. The CDB pseudo-op. Memory
increment and decrement. Special
pseudo-ops. Shift operations.
CHAPTER 7 DOUBLE AND MULTIPLE PRECISION METHODS 83
Definition of multiple precision.
Double precision addition. Double
precision subtractioOo Triple precision
subtraction. N precision addition.
Mixed precisions. The IDB operation.
Multiple precision shifts. More
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TABLE OF CONTENTS
assembler pseudo-ops.
CHAPTER 8 SOFTWARE MULTIPLICATION AND DIVISION 104
Multiplication by shift and add.
Multiplication by special constants.
The product of eight bit magnitudes.
Multiplication of signed numbers.
Double precision multiplication.
Divisor, dividend, quotient and
remainder. Binary division. The divide
fault condition. Multiple precision
division.
CHAPTER 9 SUBROUTINES AND THE STACK POINTER 122
The stack pointer. Pushing and pulling
stack data. Loading the stack pointer.
PSW bit locations. Subroutines. A
double mUltiply subroutine. A validity
check routine. Use of the stack in
computed jumps. Argument transfer.
CHAPTER 10 ADDRESSING ARRAYS AND TABLES 144
Definition of an array. Tables. Data
generating pseudo-ops. Sum of an array.
Inverting an array in memory. Sorting.
The "bubble" sort. Simple table lookup.
Special table lookup cases. The
displacement. Self modifying code.
CHAPTER 11 PROGRAMMED INPUT/OUTPUT 162
Device address. Ready flags. Clearing
the ready flag. Symbolic I/O addresses.
Peripheral status word. A parallel
printer driver. Memory mapped I/O. The
Apple screen addressing scheme.
Scrolling the screen. Table of ASCII
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TABLE OF CONTENTS
character codes.
CHAPTER 12 6502 DECIMAL ARITHMETIC 180
Use of SED and CLD. BCD addition.
Double precision BCD addition. A
decimal mode "trick". BCD subtraction.
Double precision BCD subtraction. Tens
complemen t arithmetic. Considerations
in BCD mUltiplication and division.
CHAPTER 13 FLOATING POINT ARITHMETIC 188
Components of a floating point number.
Floating point addition. The guard
digit. Loss of precision due to pre
shift. Normalization of floating point
numbers. Variability of result with
order of addition. Binary floating
point. A floating addition for the
6502. ''Noisy mode" arithmetic. Range of
floating point numbers. Alternate
floating point forms.
CHAPTER 14 NUMBER BASE CONVERSIONS 205
Conversion of BCD integer to binary.
Conversion by successive mUltiplication
by ten. Decimal validity check.
Conversion to double precision integer.
Decimal fraction to binary. Conversion
of signed numbers. Binary integer to
BCD. Binary fraction to BCD fraction.
Radix deflation method for conversion
of floating point numbers.
CHAPTER 15 GENERATION AND USE OF RANDOM NUMBERS 223
Fundamental properties of pseudorandom
numbers. Determination of the value of
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