Power Efficient Arithmetic Circuits for Application Specific Processors

150 Pages·00.72 MB·English

Power Efficient Arithmetic Circuits for
Application Specific Processors
Georgios Plakaris
Kgs. Lyngby 2003
IMM-THESIS-2003-29
Power Efficient Arithmetic

Circuits for Application

Specific Processors

Georgios Plakaris

Kgs. Lyngby 2003
Technical University of Denmark
Informatics and Mathematical Modelling
Building 321, DK-2800 Lyngby, Denmark
Phone [phone], Fax [phone]
[email protected]
www.imm.dtu.dk

IMM-THESIS: ISSN 1601-233X
i
Preface
With this thesis I (cid:12)nalize my Master of Science studies in Computer Systems Engineering
at the Technical University of Denmark.
The thesis has been carried out at the division of Computer Science and Engineering at the
department of Informatics and Mathematical Modeling at DTU under the supervision of
associate professor Jens Spars(cid:28) to whom I am grateful for many reasons. To begin with,
he was the (cid:12)rst Danish person I met at a conference in 1999, where I was working as a
secretary. This is how I found out about DTU in the (cid:12)rst place. I think, he still (cid:12)nds my
coming here an odd decision. However, the whole experience has been very \educational"
in every way.
Asasupervisorhehasalwaysbeenavailable, responsivenomatterhowtrivialmyquestions
may have been, and supportive to my e(cid:11)orts. I would also like to thank him for sponsoring
mygoingtotheseminar\Designoflow-powerdigitalcircuits: Techniquesandtools"o(cid:11)ered
at the Technical University of Turin, Italy, as part of the INTRALED program that o(cid:11)ers
training in Low-Power Design. This seminar has been a dynamic kick-o(cid:11) to my project.
I would also like to thank Tone for her being with me and making my life better. Her
support in making this project complete has been invaluable.
Last, I would like to express my gratitude to my parents for everything they have done for
me. It has not been easy for them to (cid:12)nance my studies for 8 years now, but they really
think they are making a good investment; I guess I should thank them in person.
Lyngby, 31 March, 2003
Georgios Plakaris
ii
iii
Abstract
This thesis presents a study on RT level power optimization techniques in terms of their
applicability on data-(cid:13)ow intensive data path designs and their e(cid:14)ciency.
The dynamic power management techniques of clock gating and operand isolation are in-
vestigated and their e(cid:14)ciency evaluated by sample designs. Although, clock gating by itself
o(cid:11)ers signi(cid:12)cant power savings at low overhead in sequential blocks, it is not always the
case that hold conditions can be extracted when input registers are shared among several
resources. Latch based operand isolation, was also found quite e(cid:11)ective, though savings are
o(cid:11)set by the high overhead; evened out in case of the gate-based implementation for 32bit
adder/subtractor units.
Fine clock gating is proposed as an approach that merges the merits of both methods
and yields the highest power savings and the least performance degradation, for the same
overhead.
The static RTL power optimization methods proposed are: power sensitive implementation
selection and retiming.
The use of carry-save arithmetic to eliminate carry propagation in datapaths is deployed
to improve timing slack and provide larger margins for the performance-power trade-o(cid:11) in
other parts of the design.
The proposed methods are escorted by sample design examples to illustrate their e(cid:14)ciency.
Further, by closely controlling unnecessary switching activity the overhead of sharing re-
sources among operations of varying complexity is reduced.
Themethodsproposedaresuitableforasynthesis-baseddesign(cid:13)owandachieveperformance
comparable to custom application speci(cid:12)c processors.
KEYWORDS: Low-power, power e(cid:14)cient arithmetic, operand isolation, dynamic power
management.
iv
v
Contents
1 Introduction 1
1.1 Motivation and Aim of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Application Speci(cid:12)c Processors (ASPs) . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Power Saving Techniques in a Top-Down Design Flow . . . . . . . . . . . . . 3
1.3.1 Power Dissipation in Synchronous Digital Circuits . . . . . . . . . . . 3
1.3.2 Low Power Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization of Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Part I Low-Power Design at the RT Level 7
2 Power Reduction in RT-Level 9
2.1 The RT Abstraction Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Decomposition of an RTL Design . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Power Consumption Guidelines in RTL Designs . . . . . . . . . . . . . 10
2.2 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 How it Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Automation of Clock Gating . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Operand Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 Automation of Isolation Logic Insertion . . . . . . . . . . . . . . . . . 15
2.3.3 Clock Gating and Operand Isolation Interaction . . . . . . . . . . . . 16
2.4 Pre-computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 Minimizing Switching Activity . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.1 Glitch Power Minimization . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.2 Retiming for Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.3 Low Power Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.4 Encoding for Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.1 Gate-Level Power Estimation Basics . . . . . . . . . . . . . . . . . . . 20
2.6.2 Gate-Level Power Estimation with SYNOPSYS Power Compiler . . . 21
vi CONTENTS
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Experiment 1: A Complex Arithmetic Unit 25
3.1 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Design Speci(cid:12)cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Test Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5 Operand Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 E(cid:14)cient Operand Isolation 37
4.1 Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 Latch-Based Operand Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 Master-Slave Latch Operand Isolation . . . . . . . . . . . . . . . . . . . . . . 38
4.4 Fine Clock Gating Operand Isolation . . . . . . . . . . . . . . . . . . . . . . . 39
4.5 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part II Arithmetic in a Synthesis-Based Design Flow 43
5 Arithmetic at the RT Level 45
5.1 A Review of Arithmetic Components . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.2 Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Using Standard Cell Design-Ware Components . . . . . . . . . . . . . . . . . 49
5.2.1 Synthesis-Based Design Flow . . . . . . . . . . . . . . . . . . . . . . . 49
5.2.2 Handles to Design-Ware Components . . . . . . . . . . . . . . . . . . 50
5.3 Evaluating Synopsys Design-ware Library . . . . . . . . . . . . . . . . . . . . 53
5.3.1 Performance of Design-ware Arithmetic Components . . . . . . . . . . 53
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6 Experiment 2: An E(cid:14)cient MAC Unit 57
6.1 The Benchmark MAC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 A Carry-save MAC Unit (CS-MAC) . . . . . . . . . . . . . . . . . . . . . . . 58
6.3 Pipelining the MAC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.1 Using a Public Available Library . . . . . . . . . . . . . . . . . . . . . 60
6.4 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Part III The Multi-Datatype Multiply-Accumulate Unit 63
7 Experiment 3: A Multi-Datatype MAC Unit (MD-MAC) 65
7.1 Design Speci(cid:12)cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CONTENTS vii
7.2 Block Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2.1 Allocation of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2.2 Sharing Addition Functionality . . . . . . . . . . . . . . . . . . . . . . 68
7.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.3.1 Power and Delay Optimization . . . . . . . . . . . . . . . . . . . . . . 69
7.3.2 The Shared Add/Sub Functional Unit . . . . . . . . . . . . . . . . . . 70
7.3.3 32bit Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.3.4 Weighted Addition of the Sub-products in MFI . . . . . . . . . . . . . 73
7.3.5 Output Multiplexing Functionality . . . . . . . . . . . . . . . . . . . . 75
7.4 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.4.1 Area and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.4.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8 Conclusions 79
8.1 Optimization techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.1.1 Switching Activity and Datapath Architecture . . . . . . . . . . . . . 79
8.1.2 Dynamic Power Optimization Techniques . . . . . . . . . . . . . . . . 80
8.1.3 Static Power Optimization Techniques . . . . . . . . . . . . . . . . . . 80
8.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
References 81
Appendices 85
A Source Code 87
A.1 Experiment 1: A Complex Arithmetic Unit . . . . . . . . . . . . . . . . . . . 87
A.1.1 The testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
A.1.2 The clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
A.1.3 The opcode generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.4 The design utilities package . . . . . . . . . . . . . . . . . . . . . . . . 90
A.1.5 The simulation utilities package . . . . . . . . . . . . . . . . . . . . . . 90
A.1.6 The top level design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.1.7 The design testbench. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
A.1.8 The multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
A.1.9 The subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.1.10 The adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.1.11 The design used in \PLAIN", \REG EN" and ‘CLK GATED" . . . . 96
A.1.12 The design used in \OP ISOL" and \CLK GATED OP ISOL" . . . . 98
A.1.13 The design used in \‘CLK GATED OP ISOL OPT" . . . . . . . . . . 101