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Post-Silicon Validation and Debug PDF

393 Pages·2019·17.212 MB·English
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Prabhat Mishra · Farimah Farahmandi Editors Post-Silicon Validation and Debug Post-Silicon Validation and Debug Prabhat Mishra Farimah Farahmandi (cid:129) Editors Post-Silicon Validation and Debug 123 Editors PrabhatMishra Farimah Farahmandi Department ofComputer andInformation Department ofComputer andInformation ScienceandEngineering ScienceandEngineering University of Florida University of Florida Gainesville, FL,USA Gainesville, FL,USA ISBN978-3-319-98115-4 ISBN978-3-319-98116-1 (eBook) https://doi.org/10.1007/978-3-319-98116-1 LibraryofCongressControlNumber:2018950784 ©SpringerNatureSwitzerlandAG2019 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpart of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission orinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar methodologynowknownorhereafterdeveloped. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publicationdoesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfrom therelevantprotectivelawsandregulationsandthereforefreeforgeneraluse. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authorsortheeditorsgiveawarranty,expressorimplied,withrespecttothematerialcontainedhereinor for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictionalclaimsinpublishedmapsandinstitutionalaffiliations. ThisSpringerimprintispublishedbytheregisteredcompanySpringerNatureSwitzerlandAG Theregisteredcompanyaddressis:Gewerbestrasse11,6330Cham,Switzerland Preface Inourday-to-day activities, we interact with awidevariety ofcomputing systems. When we use desktops or laptops, we are aware of the fact that these systems are computing something for us. However, in many systems, the computing is embedded in them, such as cyber-physical systems and Internet-of-Things (IoT) devices. When we drive a car or fly in an airplane, many computing devices seamlesslyworktogethertoensureapleasantandsafejourney.Similarly,whenwe perform any financial transaction or share personal details using a smartphone, embedded computing devices try to ensure the security and privacy of these transactions. Can we assume that these computing devices are correct by con- struction and therefore we can safely rely on them? A short answer is that no one can prove the absolute infallibility of today’s computing systems. This book pro- videsaclearinsightintothefundamentalchallengesassociatedwithvalidationand debugofcomputingsystems.Thisbookalsoprovideseffectivesolutionstoaddress these challenges. Mostofthesecomputingsystemsconsistofsoftware(applicationprograms), firmware, and hardware. The brain behind these computing systems is called System-on-Chip (SoC). A typical SoC includes one or more processor cores, coprocessors, caches, memory, controllers, converters, peripherals, input/output devices, sensors, and so on. To understand why SoC validation is so challenging, let us consider one of the simplest components in a SoC—an adder. An adder adds two input values and produces the result. Typically, the input values are 64-bitintegers.Therefore,toverifythisadder,wehavetosimulateseveraltrillions (264(cid:1)264)oftestvectors.Clearly,itisinfeasibletoapplytrillionsoftestvectorsto verifyanadder.Ifwecannotcompletelyverifyasimpleadder,whatisthehopethat we can verify complex SoCs. During the design stage (before fabrication), pre-silicon validation techniques try to identify and fix functional errors as well as nonfunctional requirements. In spite of extensive efforts, it is not always possible to detect all the errors during pre-silicon validation. Post-silicon validation is used to detect design flaws including the escaped functional errors as well as nonfunctional requirements v vi Preface (suchassecurityvulnerabilities).Post-siliconvalidationiswidelyacknowledgedas amajorbottleneckforcomplexSoCdesigns.Variousindustrialstudiesindicatethat the post-silicon validation effort consumes more than 50% of an SoC’s overall design effort. To understand why post-silicon validation is challenging, consider a real-world post-silicon bug. Consider a scenario when a secure firmware is getting executed in a processor pipeline and an asynchronous reset disables the locking mechanism,whichissupposedtorestrictallunauthorizedaccessesduringfirmware execution. Once lock is disabled, a user application can access the unencrypted firmware from the instruction cache. After painful debugging for several days, the problem turned out to be that the instruction memory was not cleared after the asynchronousreset.Itisimportanttohighlightingthreeimportantfactsatthispoint. (cid:129) EscapefromPre-silicon:Inthiscase,itwasinfeasibleforpre-siliconvalidation to cover all possible reset sequences in an automotive SoC consisting of approximately 200 Intellectual Property (IP) blocks, 20 reset domains, and a total offew thousand reset signals. (cid:129) LongDebugTime:Therearemanyreasonsforlongdebuginthiscase.First,the error was reported in a very different context. Next, setting up the system to reproduce the failure is a tedious process involving many trials and errors. Finally, it was time-consuming to localize the error due to the very limited observability of the internal signals. To understand this better, think of the complexity of debugging software consisting of millions of lines. In case of software debug, you can observe the values of any of the millions of variables during the execution. In case of post-silicon debug, you have limited or no visibilityatall.Inotherwords,youhavetodebugaverycomplexscenarioina billion-gate SoC with visibility of few hundred signals through in-built trace buffer. (cid:129) Complex Interactions: The SoC design is very complex with too many com- ponents interacting with firmware and software. In this example, the integrity of the circuit is compromised by unauthorized access to the unencrypted firm- ware. The vulnerability needs to be identified and fixed during post-silicon debug.Thedebugcomplexityisexpectedtogetworseastheindustrycontinues to move to even smaller geometries. This book describes the fundamental challenges associated with post-silicon vali- dation and debug of SoCs. It also covers the state-of-the-art techniques as well as ongoingresearcheffortstodrasticallyreducetheoverallpost-siliconvalidationand debugeffort.ThefirstchapterprovidesanoverviewofSoCdesignmethodologyand highlightsthechallengesinpost-siliconvalidationanddebug.Thenextfivechapters describe efficient techniques to design debug architecture including on-chip instru- mentation and signal selection. Chapters 7–10 present effective techniques to gen- eratetestsandassertions.Thenextfivechaptersprovideautomatedapproachesfor localizing, detecting, and fixing post-silicon errors. Chapters 16–17 describe post-silicon validation efforts using two case studies, a network-on-chip, and IBM Preface vii Power8 processor. The next chapter discusses the inherent conflict between design-for-debugandsecurityvulnerabilities.Finally,Chap.19concludesthebook with adiscussionon futurepost-silicon debugchallenges andopportunities. Gainesville, Florida, USA Prabhat Mishra Farimah Farahmandi Acknowledgements Thisbookwouldnotbepossiblewithoutthecontributionsofmanyresearchersand expertsinthefieldofpost-siliconvalidationanddebug.Wewouldliketogratefully acknowledge the contributions from the following authors who have contributed book chapters: (cid:129) Alif Ahmed, University of Florida, USA (cid:129) Amir Nahir, Amazon, Israel (cid:129) Dr. Azadeh Davoodi, University of Wisconsin, USA (cid:129) Dr. Debapriya Chatterjee, IBM, USA (cid:129) Dr. Doowon Lee, University of Michigan, USA (cid:129) Dr. Kai Cong, Intel, USA (cid:129) Dr. Kamran Rahmani, Box, USA (cid:129) Dr. Kanad Basu, New York University, USA (cid:129) Dr. Pouya Taatizadeh, Synopsys, Canada (cid:129) Dr. Sandeep Chandran, Indian Institute of Technology, Delhi, India (cid:129) Dr. Xiaobing Shi, McMaster University, Canada (cid:129) Dr. Yuanwen Huang, VMware, USA (cid:129) Hillel Mendelson, IBM, Israel (cid:129) Qinhao Wang, University of Tokyo, Japan (cid:129) Yusuke Kimura, University of Tokyo, Japan (cid:129) Prof. Fei Xie, Portland State University, USA (cid:129) Prof. Georg Weissenbacher, TU Wien, Austria (cid:129) Prof. Masahiro Fujita, University of Tokyo, Japan (cid:129) Prof. Nicola Nicolici, McMaster University, Canada (cid:129) Prof. Preeti Ranjan Panda, Indian Institute of Technology, Delhi, India (cid:129) Prof. Sandip Ray, University of Florida, USA (cid:129) Prof. Sharad Malik, Princeton University, USA (cid:129) Prof. Valeria Bertacco, University of Michigan, USA ix x Acknowledgements (cid:129) Subodha Charles, University of Florida, USA (cid:129) Tom Kolan, IBM, Israel (cid:129) Vitali Sokhin, IBM, Israel (cid:129) Yangdi Lyu, University of Florida, USA This work was partially supported by National Science Foundation under grant CCF-1218629.Anyopinions,findings,conclusions,orrecommendationspresented inthisbookarethoseoftheauthorsanddonotnecessarilyreflecttheviews ofthe National Science Foundation. Contents Part I Introduction 1 Post-Silicon SoC Validation Challenges. . . . . . . . . . . . . . . . . . . . . . 3 Farimah Farahmandi and Prabhat Mishra Part II Debug Infrastructure 2 SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sandip Ray 3 Structural Signal Selection for Post-Silicon Validation . . . . . . . . . . 33 Kanad Basu 4 Simulation-Based Signal Selection. . . . . . . . . . . . . . . . . . . . . . . . . . 57 Debapriya Chatterjee and Valeria Bertacco 5 Hybrid Signal Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Azadeh Davoodi 6 Post-Silicon Signal Selection Using Machine Learning . . . . . . . . . . 87 Alif Ahmed, Kamran Rahmani and Prabhat Mishra Part III Generation of Tests and Assertions 7 Observability-Aware Post-Silicon Test Generation . . . . . . . . . . . . . 111 Farimah Farahmandi and Prabhat Mishra 8 On-Chip Constrained-Random Stimuli Generation. . . . . . . . . . . . . 125 Xiaobing Shi and Nicola Nicolici 9 Test Generation and Lightweight Checking for Multi-core Memory Consistency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Doowon Lee and Valeria Bertacco xi

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