PIC16(L)F1717/8/9 Data Sheet

483 Pages·2015·6.18 MB·English

by  Microchip Technology Inc.

PIC16(L)F1717/8/9
Cost-Effective 8-Bit Intelligent Analog Flash Microcontrollers
Description:
PIC16(L)F1717/8/9 microcontrollers combine Intelligent Analog integration with low cost and extreme low power (XLP)
to suit a variety of general purpose applications. These 28-pin and 40-pin devices deliver on-chip op amps, Core
Independent Peripherals (CLC, NCO and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased
design flexibility.
Core Features: Digital Peripherals:
• C Compiler Optimized RISC Architecture • Configurable Logic Cell (CLC):
• Only 49 Instructions - Integrated combinational and sequential logic
• Operating Speed: • Complementary Output Generator (COG):
- 0-32 MHz clock input - Rising/falling edge dead-band control/
- 125 ns minimum instruction cycle blanking
• Interrupt Capability • Numerically Controlled Oscillator (NCO):
• 16-Level Deep Hardware Stack - Generates true linear frequency control and
• Up to Four 8-Bit Timers increased frequency resolution
• One 16-Bit Timer - Input Clock: 0 Hz < FNCO < 32 MHz
• Power-on Reset (POR) - Resolution: FNCO/220
• Power-up Timer (PWRT) • Capture/Compare/PWM (CCP) module
• Low-Power Brown-out Reset (LPBOR) • PWM: Two 10-Bit Pulse-Width Modulators
• Programmable Watchdog Timer (WDT) up to • Serial Communications:
256s - SPI, I2C, RS-232, RS-485, LIN compatible
• Programmable Code Protection - Auto-Baud Detect, auto-wake-up on start
• Up to 35 I/O Pins and One Input Pin:
Memory:
- Individually programmable pull-ups
• Up to 16 Kwords Flash Program Memory
- Slew rate control
• Up to 2048 Bytes Data SRAM Memory
- Interrupt-on-Change with edge-select
• Direct, Indirect and Relative Addressing modes
• Peripheral Pin Select (PPS):
• High-Endurance Flash (HEF):
- Enables pin mapping of digital I/O
- 128B of nonvolatile data storage
- 100K Erase/Write cycles Intelligent Analog Peripherals:
• Operational Amplifiers:
Operating Characteristics:
- Two configurable rail-to-rail op amps
• Operating Voltage Range:
- Selectable internal and external channels
- 1.8V to 3.6V (PIC16LF1717/8/9)
- 2 MHz gain bandwidth product
- 2.3V to 5.5V (PIC16F1717/8/9)
• High-Speed Comparators:
• Temperature Range:
- Up to two comparators
- Industrial: -40°C to 85°C
- 50 ns response time
- Extended: -40°C to 125°C
- Rail-to-rail inputs
eXtreme Low-Power (XLP) Features: • 10-Bit Analog-to-Digital Converter (ADC):
• Sleep mode: 50 nA @ 1.8V, typical - Up to 28 external channels
• Watchdog Timer: 500 nA @ 1.8V, typical - Conversion available during Sleep
• Secondary Oscillator: 500 nA @ 32 kHz - Temperature indicator
• Operating Current: • Zero-Cross Detector (ZCD):
- 8 uA @ 32 kHz, 1.8V, typical - Detect when AC signal on pin crosses
- 32 uA/MHz @ 1.8V, typical ground
• 8-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Internal connections to comparators, op
amps, Fixed Voltage Reference (FVR) and
ADC
• Internal Voltage Reference module
 2014-2015 Microchip Technology Inc. DS40001740B-page 1
PIC16(L)F1717/8/9
Clocking Structure: Programming/Debug Features:
• 16 MHz Internal Oscillator Block: • In-Circuit Debug Integrated On-Chip
- ±1% at calibration • Emulation Header for Advanced Debug:
- Selectable frequency range from 0 to 32 MHz - Provides trace, background debug and up to
• 31 kHz Low-Power Internal Oscillator 32 hardware break points
• External Oscillator Block with: • In-Circuit Serial Programming™ (ICSP™) via Two
- Three crystal/resonator modes up to 20 MHz Pins
- Two external clock modes up to 20 MHz
• Fail-Safe Clock Monitor
• Two-Speed Oscillator Start-up
• Oscillator Start-up Timer (OST)
PIC16(L)F171X Family Types
h
s
x y a
Device Data Sheet Inde Program MemorFlash (words) Data SRAM(bytes) gh Endurance Fl (bytes) (2)I/Os 10-bit ADC (ch) 5/8-bit DAC High-Speed/Comparators Op Amp Zero Cross Timers(8/16-bit) CCP PWM COG EUSART 2MSSP (IC/SPI) CLC NCO PPS (1)Debug XLP
Hi
PIC16(L)F1713 (1) 4096 512 128 25 17 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y
PIC16(L)F1716 (1) 8192 1024 128 25 17 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y
PIC16(L)F1717 (2) 8192 1024 128 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y
PIC16(L)F1718 (2) 16384 2048 128 25 17 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y
PIC16(L)F1719 (2) 16384 2048 128 36 28 1/1 2 2 1 4/1 2 2 1 1 1 4 1 Y I/E Y
Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001726 PIC16(L)F1713/6 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.
2: DS40001740 PIC16(L)F1717/8/9 Data Sheet, 28/40-Pin Flash, 8-bit Microcontrollers.
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001740B-page 2  2014-2015 Microchip Technology Inc.
PIC16(L)F1717/8/9
Pin Diagrams
FIGURE 1: 28-PIN SPDIP, SOIC, SSOP
VPP/MCLR/RE3 1 28 RB7
RA0 2 27 RB6
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
RA4 6 23 RB2
8
RA5 7 71 22 RB1
1
VSS 8 )F 21 RB0
L
RA7 9 6( 20 VDD
1
RA6 10 C 19 VSS
RC0 11 PI 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5
RC3 14 15 RC4
Note: See Table1 for the pin allocation table.
FIGURE 2: 28-PIN (U)QFN
P
P
V
/R
L
C
M
10 3/ 7654
AA E BBBB
RR R RRRR
8 7 6 5 4 3 2
2 2 2 2 2 2 2
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3 19 RB1
PIC16(L)F1718
RA5 4 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
0 1 2 3 4
8 9 1 1 1 1 1
0 1 2 345 6
C C C CCC C
R R R RRR R
Note: See Table1 for the pin allocation table.
 2014-2015 Microchip Technology Inc. DS40001740B-page 3
D TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1718) P
S
4
0001740B-p (2)I/O PDIP,SOIC,(cid:54)SSOP QFN, UQFN ADC Reference Comparator Op Amp DAC Zero Cross Timers CCP NCO PWM COG MSSP EUSART CLC Interrupt Pull-up Basic IC16
ag C1IN0- (
e RA0 2 27 AN0 CLCIN0(1) IOC Y L
4 C2IN0-
C1IN1- )
RA1 3 28 AN1 OPA1OUT CLCIN1(1) IOC Y F
C2IN1-
1
C1IN0+
RA2 4 1 AN2 V - DAC1OUT1 IOC Y
(cid:53)(cid:40)(cid:41) C2IN0+ 7
RA3 5 2 AN3 V(cid:53)(cid:40)(cid:41)+ C1IN1+ IOC Y 1
RA4 6 3 OPA1IN+ T0CKI(1) IOC Y 7
RA5 7 4 AN4 OPA1IN- DAC2OUT1 nSS(1) IOC Y /
OSC2 8
RA6 10 7 IOC Y
CLKOUT /
9
OSC1
RA7 9 6 IOC Y
CLKIN
RB0 21 18 AN12 C2IN1+ ZCD COG1IN(1) INT(1) Y
IOC
C1IN3-
RB1 22 19 AN10 OPA2OUT IOC Y
C2IN3-
RB2 23 20 AN8 OPA2IN- IOC Y
C1IN2-
RB3 24 21 AN9 OPA2IN+ IOC Y
C2IN2-
RB4 25 22 AN11 IOC Y
RB5 26 23 AN13 T1G(1) IOC Y
RB6 27 24 CLCIN2(1) IOC Y ICSPCLK
DAC1OUT2
RB7 28 25 CLCIN3(1) IOC Y ICSPDAT
DAC2OUT2

2 RC0 11 8 T1CKI(1) IOC Y
01 SOSCO
4-2 RC1 12 9 SOSCI CCP2(1) IOC Y
01 RC2 13 10 AN14 CCP1(1) IOC Y
5
M RC3 14 11 AN15 (cid:54)(cid:38)(cid:47)(cid:18)SCK(1) IOC Y
ic Note1:Default peripheral input. Alternatepinscanbe selected as the peripheral input withthe PPS inputselectionregisters.
ro
c 2: Allpindigital outputs default to PORTlatchdata.Alternateoutputscanbe selected as the peripheral digital output withthe PPS outputselectionregisters.
h
ip 3:Theseperipheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
T
e 4: Alternateoutputsareexcluded from solidshaded areas.
c
hn 5: Alternateinputsareexcluded from dotshadedareas.
o
lo
g
y
In
c
.
 TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1718) (CONTINUED)
2
0
14-2015 Mic (2)I/O PDIP,SOIC,(cid:54)SSOP QFN, UQFN ADC Reference Comparator Op Amp DAC Zero Cross Timers CCP NCO PWM COG MSSP EUSART CLC Interrupt Pull-up Basic
ro SDI(1)
c RC4 15 12 AN16 IOC Y
h SDA(1)
ip
T RC5 16 13 AN17 IOC Y
ec RC6 17 14 AN18 CK(3) IOC Y
h
no RC7 18 15 AN19 RX(3) IOC Y
lo
g MCLR
y In RE3 1 26 IOC Y V(cid:51)(cid:51)
c. V(cid:39)(cid:39) 20 17 V(cid:39)(cid:39)
V 8 5 V(cid:54)(cid:54)
(cid:54)(cid:54) 19 16
OUT(4) C1OUT C2OUT CCP1 CCP2 NCOOUT(cid:20) PWM3OUT PWM4OUT COG1A COG1B COG1C COG1D (3)SDA (3)SCK/SCL SDO TX/CK (3)DT CLC4OUT CLC3OUT CLC2OUT CLC1OUT
IN(5) T1G T1CKI T0CKI CCP1 CCP2 COG1IN SDI (3)CK/SCL SS (3)RX CK CLCIN0 CLCIN1 CLCIN2 CLCIN3 INT
S
Note1:Default peripheral input. Alternatepinscanbe selected as the peripheral input withthe PPS inputselectionregisters.
2: Allpindigital outputs default to PORTlatchdata.Alternateoutputscanbe selected as the peripheral digital output withthe PPS outputselectionregisters.
3: Theseperipheral functions are bidirectional. The output pin selections must be the same as the input pin selections. P
4: Alternateoutputsareexcluded from solidshaded areas.
I
5: Alternateinputsareexcluded from dotshadedareas. C
1
6
(
L
)
F
1
D
S 7
4
0
0 1
0
17 7
4
0 /
B-p 8
ag /
e 9
5
PIC16(L)F1717/8/9
FIGURE 3: 40-PIN PDIP
VPP/MCLR/RE3 1 40 RB7/ICSPDAT
RA0 2 39 RB6/ICSPCLK
RA1 3 38 RB5
RA2 4 37 RB4
RA3 5 36 RB3
RA4 6 35 RB2
RA5 7 34 RB1
RE0 8 33 RB0
RE1 9 7/9 32 VDD
RE2 10 71 31 VSS
1
VDD 11 F) 30 RD7
VSS 12 6L( 29 RD6
1
RA7 13 C 28 RD5
PI
RA6 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
RC2 17 24 RC5
RC3 18 23 RC4
RD0 19 22 RD3
RD1 20 21 RD2
Note: See Table2 for the pin allocation table.
FIGURE 4: 40-PIN UQFN (5X5)
6543210321
CCCDDDDCCC
RRRRRRRRRR
RC7 1 40 39 38 37 36 35 34 33 32 31
RD4 2 30 RC0
RD5 3 29 RA6
RD6 4 28 RA7
RD7 5 27 VSS
PIC16L(F)1717/9
VSS 6 26 VDD
VDD 7 25 RE2
RB0 8 24 RE1
RB1 9 23 RE0
RB2 10 22 RA5
21 RA4
1 2 3 4 5 6 7 8 9 0
1 1 1 1 1 1 1 1 1 2
3456730123
BBBBBEAAAA
RRRRRRRRRR
K/T/R/
LAL
CDC
PPM
CSCS/P
IIVP
Note: See Table2 for the pin allocation table.
DS40001740B-page 6  2014-2015 Microchip Technology Inc.
PIC16(L)F1717/8/9
FIGURE 5: 44-PIN TQFP (10X10)
6543210321
CCCDDDDCCCC
RRRRRRRRRRN
432 1 0 9 8 7 6 5 4
444 4 4 3 3 3 3 3 3
RC7 1 33 NC
RD4 2 32 RC0
RD5 3 31 RA6
RD6 4 30 RA7
RD7 5 29 VSS
VSS 6 PIC16(L)F1717/9 28 VDD
VDD 7 27 RE2
RB0 8 26 RE1
RB1 9 25 RE0
RB2 10 24 RA5
23 RA4
RB3 11
2 34 5 678 9 012
1 11 1 111 1 222
C C456730123
N NBBBBEAAAA
RRRRRRRRR
K/T/R/
LAL
CDC
PPM
CSCS/P
IIVP
Note: See Table2 for the pin allocation table.
 2014-2015 Microchip Technology Inc. DS40001740B-page 7
D TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9) P
S
40001740B-p (2)I/O PDIP TQFP UQFN ADC Reference Comparator Op Amp DAC Zero Cross Timers CCP NCO PWM COG MSSP EUSART CLC Interrupt Pullup Basic IC16
age 8 RA0 2 19 17 AN0 CC12IINN00-- CLCIN0(1) IOC Y (L
C1IN1- )
RA1 3 20 18 AN1 OPA1OUT CLCIN1(1) IOC Y F
C2IN1-
C1IN0+ 1
RA2 4 21 19 AN2 V - DAC1OUT1 IOC Y
(cid:53)(cid:40)(cid:41) C2IN0+ 7
RA3 5 22 20 AN3 V(cid:53)(cid:40)(cid:41)+ C1IN1+ IOC Y 1
RA4 6 23 21 OPA1IN+ T0CKI(1) IOC Y 7
RA5 7 24 22 AN4 OPA1IN- DAC2OUT1 nSS(1) IOC Y
/
OSC2 8
RA6 14 31 29 IOC Y
CLKOUT /
9
OSC1
RA7 13 30 28 IOC Y
CLKIN
RB0 33 8 8 AN12 C2IN1+ ZCD COG1IN(1) INT(1) Y
IOC
C1IN3-
RB1 34 9 9 AN10 OPA2OUT IOC Y
C2IN3-
RB2 35 10 10 AN8 OPA2IN- IOC Y
C1IN2-
RB3 36 11 11 AN9 OPA2IN+ IOC Y
C2IN2-
RB4 37 14 12 AN11 IOC Y
RB5 38 15 13 AN13 T1G(1) IOC Y
RB6 39 16 14 CLCIN2(1) IOC Y ICSPCLK
DAC1OUT2
RB7 40 17 15 CLCIN3(1) IOC Y ICSPDAT
DAC2OUT2

201 RC0 15 32 30 STO1CSCKOI(1) IOC Y
4
-2 RC1 16 35 31 SOSCI CCP2(1) IOC Y
0
1 RC2 17 36 32 AN14 CCP1(1) IOC Y
5
M RC3 18 37 33 AN15 (cid:54)(cid:38)(cid:47)(cid:18)SCK(1) IOC Y
icro Note1:Defaultperipheralinput.Alternatepinscanbeselectedastheperipheralinputwiththe PPS inputselectionregisters.
ch 2:AllpindigitaloutputsdefaulttoPORTlatchdata.Alternateoutputs can be selectedastheperipheraldigitaloutputwiththePPSoutputselectionregisters.
ip T 3:Theseperipheralfunctionsarebidirectional.Theoutputpinselectionsmustbethesameastheinputpinselections.
e 4:Alternateoutputsareexcludedfromsolidshadedareas.
c
h
n 5:Alternateinputsareexcludedfromdotshadedareas.
o
lo
g
y
In
c
.
 TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9) (CONTINUED)
2
014-2015 Mic (2)I/O PDIP TQFP UQFN ADC Reference Comparator Op Amp DAC Zero Cross Timers CCP NCO PWM COG MSSP EUSART CLC Interrupt Pullup Basic
roc RC4 23 42 38 AN16 SDI(1) IOC Y
h SDA(1)
ip
T RC5 24 43 39 AN17 IOC Y
ec RC6 25 44 40 AN18 CK(3) IOC Y
h
no RC7 26 1 1 AN19 RX(3) IOC Y
log RD0 19 38 34 AN20 Y
y
In RD1 20 39 35 AN21 Y
c. RD2 21 40 36 AN22 Y
RD3 22 41 37 AN23 Y
RD4 27 2 2 AN24 Y
RD5 28 3 3 AN25 Y
RD6 29 4 4 AN26 Y
RD7 30 5 5 AN27 Y
RE0 8 25 23 AN5 Y
RE1 9 26 24 AN6 Y
RE2 10 27 25 AN7 Y
MCLR
RE3 1 18 16 IOC Y
V
(cid:51)(cid:51)
V 11 7 7 V(cid:39)(cid:39)
(cid:39)(cid:39) 32 28 26
12 6 6 V
V (cid:54)(cid:54) P
(cid:54)(cid:54) 31 29 27
I
OUT(4) C1OUT C2OUT CCP1 CCP2 COOUT(cid:20) WM3OUT WM4OUT COG1A COG1B COG1C COG1D (3)SDA (3)CK/SCL SDO TX/CK (3)DT LC4OUT LC3OUT LC2OUT LC1OUT C1
N P P S C C C C 6
IN(5) T1G T1CKI T0CKI CCP1 CCP2 COG1IN SDI (3)CK/SCL SS (3)RX CK CLCIN0 CLCIN1 CLCIN2 CLCIN3 INT (L)F
S
Note 1: Default peripheralinput. Alternate pins can beselected as the peripheralinputwith the PPSinput selection registers. 1
D
S 2:Allpindigitaloutputs default to PORT latch data. Alternate outputs canbeselected as the peripheraldigital output with the PPSoutput selection registers. 7
4
00 3: These peripheralfunctionsarebidirectional. The output pinselections must bethe same as the input pinselections. 1
017 4: Alternate outputs areexcluded from solid shaded areas. 7
4 5: Alternate inputs areexcluded from dot shaded areas.
0 /
B-p 8
ag /
e 9
9
PIC16(L)F1717/8/9
Table of Contents
1.0 Device Overview........................................................................................................................................................................12
2.0 Enhanced Mid-Range CPU........................................................................................................................................................22
3.0 Memory Organization.................................................................................................................................................................24
4.0 Device Configuration..................................................................................................................................................................55
5.0 Resets........................................................................................................................................................................................60
6.0 Oscillator Module (with Fail-Safe Clock Monitor).......................................................................................................................68
7.0 Interrupts....................................................................................................................................................................................86
8.0 Power-Down Mode (Sleep)........................................................................................................................................................98
9.0 Watchdog Timer (WDT)...........................................................................................................................................................102
10.0 Flash Program Memory Control...............................................................................................................................................106
11.0 I/O Ports...................................................................................................................................................................................122
12.0 Peripheral Pin Select (PPS) Module........................................................................................................................................150
13.0 Interrupt-On-Change................................................................................................................................................................156
14.0 Fixed Voltage Reference (FVR)..............................................................................................................................................163
15.0 Temperature Indicator Module.................................................................................................................................................166
16.0 Comparator Module..................................................................................................................................................................168
17.0 Pulse Width Modulation (PWM)...............................................................................................................................................177
18.0 Complementary Output Generator (COG) Module...................................................................................................................184
19.0 Configurable Logic Cell (CLC)..................................................................................................................................................218
20.0 Numerically Controlled Oscillator (NCO) Module.....................................................................................................................233
21.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................242
22.0 Operational Amplifier (OPA) Modules......................................................................................................................................255
23.0 8-Bit Digital-to-Analog Converter (DAC1) Module....................................................................................................................258
24.0 5-Bit Digital-to-Analog Converter (DAC2) Module....................................................................................................................261
25.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................264
26.0 Timer0 Module.........................................................................................................................................................................268
27.0 Timer1 Module with Gate Control.............................................................................................................................................271
28.0 Timer2/4/6 Module...................................................................................................................................................................282
29.0 Capture/Compare/PWM Modules............................................................................................................................................287
30.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................295
31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................351
32.0 In-Circuit Serial Programming (ICSP™)...................................................................................................................................381
33.0 Instruction Set Summary..........................................................................................................................................................383
34.0 Electrical Specifications............................................................................................................................................................397
35.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................432
36.0 Development Support...............................................................................................................................................................454
37.0 Packaging Information..............................................................................................................................................................458
Appendix A: Data Sheet Revision History .........................................................................................................................................479
DS40001740B-page 10  2014-2015 Microchip Technology Inc.