Table Of Content

PCI Local Bus Specification Revision 2.2 December 18, 1998 Revision 2.2 REVISION REVISION HISTORY DATE 1.0 Original issue 6/22/92 2.0 Incorporated connector and expansion board specification 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95 2.2 Incorporated ECNs and improved readability 12/18/98 7KH(cid:3)3&,(cid:3)6SHFLDO(cid:3),QWHUHVW(cid:3)*URXS(cid:3)GLVFODLPV(cid:3)DOO(cid:3)ZDUUDQWLHV(cid:3)DQG(cid:3)OLDELOLW\(cid:3)IRU(cid:3)WKH(cid:3)XVH(cid:3)RI(cid:3)WKLV(cid:3)GRFXPHQW DQG(cid:3)WKH(cid:3)LQIRUPDWLRQ(cid:3)FRQWDLQHG(cid:3)KHUHLQ(cid:3)DQG(cid:3)DVVXPHV(cid:3)QR(cid:3)UHVSRQVLELOLW\(cid:3)IRU(cid:3)DQ\(cid:3)HUURUV(cid:3)WKDW(cid:3)PD\(cid:3)DSSHDU LQ(cid:3)WKLV(cid:3)GRFXPHQW(cid:15)(cid:3)QRU(cid:3)GRHV(cid:3)WKH(cid:3)3&,(cid:3)6SHFLDO(cid:3),QWHUHVW(cid:3)*URXS(cid:3)PDNH(cid:3)D(cid:3)FRPPLWPHQW(cid:3)WR(cid:3)XSGDWH(cid:3)WKH LQIRUPDWLRQ(cid:3)FRQWDLQHG(cid:3)KHUHLQ(cid:17) &RQWDFW(cid:3)WKH(cid:3)3&,(cid:3)6SHFLDO(cid:3),QWHUHVW(cid:3)*URXS(cid:3)RIILFH(cid:3)WR(cid:3)REWDLQ(cid:3)WKH(cid:3)ODWHVW(cid:3)UHYLVLRQ(cid:3)RI(cid:3)WKH(cid:3)VSHFLILFDWLRQ(cid:17) 4XHVWLRQV(cid:3)UHJDUGLQJ(cid:3)WKH(cid:3)3&,(cid:3)VSHFLILFDWLRQ(cid:3)RU(cid:3)PHPEHUVKLS(cid:3)LQ(cid:3)WKH(cid:3)3&,(cid:3)6SHFLDO(cid:3),QWHUHVW(cid:3)*URXS(cid:3)PD\(cid:3)EH IRUZDUGHG(cid:3)WR(cid:29) 3&,(cid:3)6SHFLDO(cid:3),QWHUHVW(cid:3)*URXS (cid:21)(cid:24)(cid:26)(cid:24)(cid:3)1(cid:17)((cid:17)(cid:3).DWKU\Q(cid:3)(cid:6)(cid:20)(cid:26) +LOOVERUR(cid:15)(cid:3)2UHJRQ(cid:3)(cid:28)(cid:26)(cid:20)(cid:21)(cid:23) 3KRQH(cid:29) (cid:27)(cid:19)(cid:19)(cid:16)(cid:23)(cid:22)(cid:22)(cid:16)(cid:24)(cid:20)(cid:26)(cid:26)(cid:3)(cid:11),QVLGH(cid:3)WKH(cid:3)8(cid:17)6(cid:17)(cid:12) (cid:24)(cid:19)(cid:22)(cid:16)(cid:25)(cid:28)(cid:22)(cid:16)(cid:25)(cid:22)(cid:25)(cid:19)(cid:3)(cid:11)2XWVLGH(cid:3)WKH(cid:3)8(cid:17)6(cid:17)(cid:12) )D[(cid:29) (cid:24)(cid:19)(cid:22)(cid:16)(cid:25)(cid:28)(cid:22)(cid:16)(cid:27)(cid:22)(cid:23)(cid:23) H(cid:16)PDLO SFLVLJ#SFLVLJ(cid:17)FRP http://www.pcisig.com ’,6&/$,0(5 7KLV(cid:3)3&,(cid:3)/RFDO(cid:3)%XV(cid:3)6SHFLILFDWLRQ(cid:3)LV(cid:3)SURYLGHG(cid:3)(cid:5)DV(cid:3)LV(cid:5)(cid:3)ZLWK(cid:3)QR(cid:3)ZDUUDQWLHV(cid:3)ZKDWVRHYHU(cid:15) LQFOXGLQJ(cid:3)DQ\(cid:3)ZDUUDQW\(cid:3)RI(cid:3)PHUFKDQWDELOLW\(cid:15)(cid:3)QRQLQIULQJHPHQW(cid:15)(cid:3)ILWQHVV(cid:3)IRU(cid:3)DQ\(cid:3)SDUWLFXODU SXUSRVH(cid:15)(cid:3)RU(cid:3)DQ\(cid:3)ZDUUDQW\(cid:3)RWKHUZLVH(cid:3)DULVLQJ(cid:3)RXW(cid:3)RI(cid:3)DQ\(cid:3)SURSRVDO(cid:15)(cid:3)VSHFLILFDWLRQ(cid:15)(cid:3)RU(cid:3)VDPSOH(cid:17) 7KH(cid:3)3&,(cid:3)6,*(cid:3)GLVFODLPV(cid:3)DOO(cid:3)OLDELOLW\(cid:3)IRU(cid:3)LQIULQJHPHQW(cid:3)RI(cid:3)SURSULHWDU\(cid:3)ULJKWV(cid:15)(cid:3)UHODWLQJ(cid:3)WR(cid:3)XVH RI(cid:3)LQIRUPDWLRQ(cid:3)LQ(cid:3)WKLV(cid:3)VSHFLILFDWLRQ(cid:17)(cid:3)(cid:3)1R(cid:3)OLFHQVH(cid:15)(cid:3)H[SUHVV(cid:3)RU(cid:3)LPSOLHG(cid:15)(cid:3)E\(cid:3)HVWRSSHO(cid:3)RU RWKHUZLVH(cid:15)(cid:3)WR(cid:3)DQ\(cid:3)LQWHOOHFWXDO(cid:3)SURSHUW\(cid:3)ULJKWV(cid:3)LV(cid:3)JUDQWHG(cid:3)KHUHLQ(cid:17) $/3+$(cid:3)LV(cid:3)D(cid:3)UHJLVWHUHG(cid:3)WUDGHPDUN(cid:3)RI(cid:3)’LJLWDO(cid:3)(TXLSPHQW(cid:3)&RUSRUDWLRQ(cid:17) )LUH:LUH(cid:3)LV(cid:3)D(cid:3)WUDGHPDUN(cid:3)RI(cid:3)$SSOH(cid:3)&RPSXWHU(cid:15)(cid:3),QF(cid:17) 7RNHQ(cid:3)5LQJ(cid:3)DQG(cid:3)9*$(cid:3)DUH(cid:3)WUDGHPDUNV(cid:3)DQG(cid:3)36(cid:18)(cid:21)(cid:15)(cid:3),%0(cid:15)(cid:3)0LFUR(cid:3)&KDQQHO(cid:15)(cid:3)26(cid:18)(cid:21)(cid:15)(cid:3)DQG(cid:3)3&(cid:3)$7(cid:3)DUH(cid:3)UHJLVWHUHG WUDGHPDUNV(cid:3)RI(cid:3),%0(cid:3)&RUSRUDWLRQ(cid:17) :LQGRZV(cid:15)(cid:3)06(cid:16)’26(cid:15)(cid:3)DQG(cid:3)0LFURVRIW(cid:3)DUH(cid:3)UHJLVWHUHG(cid:3)WUDGHPDUNV(cid:3)RI(cid:3)0LFURVRIW(cid:3)&RUSRUDWLRQ(cid:17) 7ULVWDWH(cid:3)LV(cid:3)D(cid:3)UHJLVWHUHG(cid:3)WUDGHPDUN(cid:3)RI(cid:3)1DWLRQDO(cid:3)6HPLFRQGXFWRU(cid:17) 1X%XV(cid:3)LV(cid:3)D(cid:3)WUDGHPDUN(cid:3)RI(cid:3)7H[DV(cid:3),QVWUXPHQWV(cid:17) (WKHUQHW(cid:3)LV(cid:3)D(cid:3)UHJLVWHUHG(cid:3)WUDGHPDUN(cid:3)RI(cid:3);HUR[(cid:3)&RUSRUDWLRQ(cid:17) $OO(cid:3)RWKHU(cid:3)SURGXFW(cid:3)QDPHV(cid:3)DUH(cid:3)WUDGHPDUNV(cid:15)(cid:3)UHJLVWHUHG(cid:3)WUDGHPDUNV(cid:15)(cid:3)RU(cid:3)VHUYLFHPDUNV(cid:3)RI(cid:3)WKHLU(cid:3)UHVSHFWLYH(cid:3)RZQHUV(cid:17) Copyright © 1992, 1993, 1995, 1998 PCI Special Interest Group ii Revision 2.2 Contents Chapter 1 Introduction 1.1. Specification Contents............................................................................................................1 1.2. Motivation..............................................................................................................................1 1.3. PCI Local Bus Applications...................................................................................................2 1.4. PCI Local Bus Overview........................................................................................................3 1.5. PCI Local Bus Features and Benefits.....................................................................................4 1.6. Administration........................................................................................................................6 Chapter 2 Signal Definition 2.1. Signal Type Definition...........................................................................................................8 2.2. Pin Functional Groups............................................................................................................8 2.2.1. System Pins.....................................................................................................................8 2.2.2. Address and Data Pins.....................................................................................................9 2.2.3. Interface Control Pins....................................................................................................10 2.2.4. Arbitration Pins (Bus Masters Only).............................................................................11 2.2.5. Error Reporting Pins......................................................................................................12 2.2.6. Interrupt Pins (Optional) ...............................................................................................13 2.2.7. Additional Signals.........................................................................................................15 2.2.8. 64-Bit Bus Extension Pins (Optional)...........................................................................17 2.2.9. JTAG/Boundary Scan Pins (Optional)..........................................................................18 2.3. Sideband Signals..................................................................................................................19 2.4. Central Resource Functions..................................................................................................19 iii Revision 2.2 Chapter 3 Bus Operation 3.1. Bus Commands.....................................................................................................................21 3.1.1. Command Definition.....................................................................................................21 3.1.2. Command Usage Rules.................................................................................................23 3.2. PCI Protocol Fundamentals..................................................................................................26 3.2.1. Basic Transfer Control..................................................................................................26 3.2.2. Addressing.....................................................................................................................27 3.2.2.1. I/O Space Decoding................................................................................................28 3.2.2.2. Memory Space Decoding.......................................................................................28 3.2.2.3. Configuration Space Decoding...............................................................................30 3.2.3. Byte Lane and Byte Enable Usage................................................................................38 3.2.4. Bus Driving and Turnaround.........................................................................................39 3.2.5. Transaction Ordering and Posting.................................................................................40 3.2.5.1. Transaction Ordering and Posting for Simple Devices..........................................41 3.2.5.2. Transaction Ordering and Posting for Bridges.......................................................42 3.2.6. Combining, Merging, and Collapsing...........................................................................44 3.3. Bus Transactions..................................................................................................................46 3.3.1. Read Transaction...........................................................................................................47 3.3.2. Write Transaction..........................................................................................................48 3.3.3. Transaction Termination...............................................................................................49 3.3.3.1. Master Initiated Termination..................................................................................49 3.3.3.2. Target Initiated Termination ..................................................................................52 3.3.3.3. Delayed Transactions.............................................................................................61 3.4. Arbitration............................................................................................................................68 3.4.1. Arbitration Signaling Protocol......................................................................................70 3.4.2. Fast Back-to-Back Transactions....................................................................................72 3.4.3. Arbitration Parking........................................................................................................74 3.5. Latency.................................................................................................................................75 3.5.1. Target Latency...............................................................................................................75 3.5.1.1. Target Initial Latency.............................................................................................75 3.5.1.2. Target Subsequent Latency....................................................................................77 iv Revision 2.2 3.5.2. Master Data Latency......................................................................................................78 3.5.3. Memory Write Maximum Completion Time Limit......................................................78 3.5.4. Arbitration Latency.......................................................................................................79 3.5.4.1. Bandwidth and Latency Considerations.................................................................80 3.5.4.2. Determining Arbitration Latency...........................................................................82 3.5.4.3. Determining Buffer Requirements.........................................................................87 3.6. Other Bus Operations...........................................................................................................88 3.6.1. Device Selection............................................................................................................88 3.6.2. Special Cycle.................................................................................................................90 3.6.3. Address/Data Stepping..................................................................................................91 3.6.4. Interrupt Acknowledge..................................................................................................93 3.7. Error Functions.....................................................................................................................93 3.7.1. Parity Generation...........................................................................................................94 3.7.2. Parity Checking.............................................................................................................95 3.7.3. Address Parity Errors....................................................................................................95 3.7.4. Error Reporting..............................................................................................................95 3.7.4.1. Data Parity Error Signaling on PERR#..................................................................96 3.7.4.2. Other Error Signaling on SERR#...........................................................................97 3.7.4.3. Master Data Parity Error Status Bit........................................................................98 3.7.4.4. Detected Parity Error Status Bit.............................................................................98 3.7.5. Delayed Transactions and Data Parity Errors...............................................................98 3.7.6. Error Recovery..............................................................................................................99 3.8. 64-Bit Bus Extension..........................................................................................................100 3.8.1. Determining Bus Width During System Initialization................................................104 3.9. 64-bit Addressing...............................................................................................................105 3.10. Special Design Considerations.........................................................................................108 v Revision 2.2 Chapter 4 Electrical Specification 4.1. Overview............................................................................................................................113 4.1.1. 5V to 3.3V Transition Road Map................................................................................113 4.1.2. Dynamic vs. Static Drive Specification ......................................................................115 4.2. Component Specification...................................................................................................115 4.2.1. 5V Signaling Environment..........................................................................................117 4.2.1.1. DC Specifications.................................................................................................117 4.2.1.2. AC Specifications.................................................................................................118 4.2.1.3. Maximum AC Ratings and Device Protection.....................................................120 4.2.2. 3.3V Signaling Environment.......................................................................................122 4.2.2.1. DC Specifications.................................................................................................122 4.2.2.2. AC Specifications.................................................................................................123 4.2.2.3. Maximum AC Ratings and Device Protection.....................................................125 4.2.3. Timing Specification...................................................................................................126 4.2.3.1. Clock Specification..............................................................................................126 4.2.3.2. Timing Parameters................................................................................................128 4.2.3.3. Measurement and Test Conditions.......................................................................129 4.2.4. Indeterminate Inputs and Metastability.......................................................................130 4.2.5. Vendor Provided Specification....................................................................................131 4.2.6. Pinout Recommendation.............................................................................................131 4.3. System (Motherboard) Specification..................................................................................132 4.3.1. Clock Skew..................................................................................................................132 4.3.2. Reset............................................................................................................................133 4.3.3. Pull-ups........................................................................................................................136 4.3.4. Power...........................................................................................................................137 4.3.4.1. Power Requirements.............................................................................................137 4.3.4.2. Sequencing............................................................................................................137 4.3.4.3. Decoupling............................................................................................................138 4.3.5. System Timing Budget................................................................................................138 4.3.6. Physical Requirements................................................................................................141 4.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards...............141 4.3.6.2. Motherboard Impedance.......................................................................................141 vi Revision 2.2 4.3.7. Connector Pin Assignments........................................................................................142 4.4. Expansion Board Specification..........................................................................................146 4.4.1. Board Pin Assignment.................................................................................................146 4.4.2. Power Requirements....................................................................................................150 4.4.2.1. Decoupling............................................................................................................150 4.4.2.2. Power Consumption.............................................................................................150 4.4.3. Physical Requirements................................................................................................151 4.4.3.1. Trace Length Limits.............................................................................................151 4.4.3.2. Routing Recommendations for Four-Layer Expansion Boards...........................152 4.4.3.3. Impedance.............................................................................................................152 4.4.3.4. Signal Loading......................................................................................................152 Chapter 5 Mechanical Specification 5.1. Overview............................................................................................................................153 5.2. Expansion Card Physical Dimensions and Tolerances......................................................154 5.2.1. Connector Physical Description..................................................................................168 5.2.1.1. Connector Physical Requirements........................................................................176 5.2.1.2. Connector Performance Specification..................................................................177 5.2.2. Planar Implementation ................................................................................................178 Chapter 6 Configuration Space 6.1. Configuration Space Organization.....................................................................................190 6.2. Configuration Space Functions..........................................................................................192 6.2.1. Device Identification...................................................................................................192 6.2.2. Device Control.............................................................................................................193 6.2.3. Device Status...............................................................................................................196 6.2.4. Miscellaneous Registers..............................................................................................198 6.2.5. Base Addresses............................................................................................................201 6.2.5.1. Address Maps.......................................................................................................201 6.2.5.2. Expansion ROM Base Address Register..............................................................204 6.3. PCI Expansion ROMs........................................................................................................205 6.3.1. PCI Expansion ROM Contents....................................................................................206 vii Revision 2.2 6.3.1.1. PCI Expansion ROM Header Format...................................................................206 6.3.1.2. PCI Data Structure Format...................................................................................207 6.3.2. Power-on Self Test (POST) Code...............................................................................209 6.3.3. PC-compatible Expansion ROMs................................................................................209 6.3.3.1. ROM Header Extensions......................................................................................209 6.4. Vital Product Data...............................................................................................................212 6.5. Device Drivers....................................................................................................................212 6.6. System Reset......................................................................................................................213 6.7. Capabilities List..................................................................................................................213 6.8. Message Signaled Interrupts ..............................................................................................214 6.8.1. Message Capability Structure.......................................................................................214 6.8.1.1. Capability ID........................................................................................................215 6.8.1.2. Next Pointer..........................................................................................................215 6.8.1.3. Message Control...................................................................................................215 6.8.1.4. Message Address..................................................................................................217 6.8.1.5. Message Upper Address (Optional).....................................................................217 6.8.1.6. Message Data........................................................................................................218 6.8.2. MSI Operation..............................................................................................................218 6.8.2.1. MSI Transaction Termination..............................................................................220 6.8.2.2. MSI Transaction Reception and Ordering Requirements ....................................220 Chapter 7 66 Mhz PCI Specification 7.1. Introduction........................................................................................................................221 7.2. Scope..................................................................................................................................221 7.3. Device Implementation Considerations.............................................................................222 7.3.1. Configuration Space....................................................................................................222 7.4. Agent Architecture.............................................................................................................222 7.5. Protocol...............................................................................................................................222 7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition..............................................................222 7.5.2. Latency........................................................................................................................223 viii Revision 2.2 7.6. Electrical Specification.......................................................................................................223 7.6.1. Overview.....................................................................................................................223 7.6.2. Transition Roadmap to 66 MHz PCI...........................................................................224 7.6.3. Signaling Environment................................................................................................224 7.6.3.1. DC Specifications.................................................................................................225 7.6.3.2. AC Specifications.................................................................................................225 7.6.3.3. Maximum AC Ratings and Device Protection.....................................................226 7.6.4. Timing Specification...................................................................................................226 7.6.4.1. Clock Specification..............................................................................................226 7.6.4.2. Timing Parameters................................................................................................228 7.6.4.3. Measurement and Test Conditions.......................................................................229 7.6.5. Vendor Provided Specification ...................................................................................231 7.6.6. Recommendations.......................................................................................................231 7.6.6.1. Pinout Recommendations.....................................................................................231 7.6.6.2. Clocking Recommendations.................................................................................231 7.7. System (Planar) Specification............................................................................................232 7.7.1. Clock Uncertainty........................................................................................................232 7.7.2. Reset............................................................................................................................233 7.7.3. Pullups.........................................................................................................................233 7.7.4. Power...........................................................................................................................233 7.7.4.1. Power Requirements.............................................................................................233 7.7.4.2. Sequencing............................................................................................................233 7.7.4.3. Decoupling............................................................................................................233 7.7.5. System Timing Budget................................................................................................233 7.7.6. Physical Requirements................................................................................................236 7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards..........................236 7.7.6.2. Planar Impedance.................................................................................................236 7.7.7. Connector Pin Assignments........................................................................................236 7.8. Expansion Board Specifications.........................................................................................237 ix Revision 2.2 Appendix A Special Cycle Messages.......................................239 Appendix B State Machines......................................................241 Appendix C Operating Rules.....................................................251 Appendix D Class Codes...........................................................257 Appendix E System Transaction Ordering...............................267 Appendix F Exclusive Accesses...............................................279 Appendix G I/O Space Address Decoding for Legacy Devices ....................................................285 Appendix H Capability IDs..........................................................287 Appendix I Vital Product Data...................................................289 Glossary .......................................................................................297 x

ebook img

PCI Local Bus Specification, Revision 2.2 PDF

322 Pages·1998·3.658 MB·English
by  
#
Download
Upgrade Premium
Most books are stored in the elastic cloud where traffic is expensive. For this reason, we have a limit on daily download.

Download PCI Local Bus Specification, Revision 2.2 PDF Free - Full Version

by Unknow| 1998| 322 pages| 3.658| English

Download PCI Local Bus Specification, Revision 2.2 by in PDF format completely FREE. No registration required, no payment needed. Get instant access to this valuable resource on PDFdrive.to!

Free Download PDF

About PCI Local Bus Specification, Revision 2.2

No description available for this book.

Detailed Information

Author:Unknown
Publication Year:1998
ISBN:3271620
Pages:322
Language:English
File Size:3.658
Format:PDF
Price:FREE
Download Free PDF

Safe & Secure Download - No registration required

Why Choose PDFdrive for Your Free PCI Local Bus Specification, Revision 2.2 Download?

  • 100% Free: No hidden fees or subscriptions required for one book every day.
  • No Registration: Immediate access is available without creating accounts for one book every day.
  • Safe and Secure: Clean downloads without malware or viruses
  • Multiple Formats: PDF, MOBI, Mpub,... optimized for all devices
  • Educational Resource: Supporting knowledge sharing and learning

Free Books Similar to PCI Local Bus Specification, Revision 2.2

Frequently Asked Questions

Is it really free to download PCI Local Bus Specification, Revision 2.2 PDF?

Yes, on https://PDFdrive.to you can download PCI Local Bus Specification, Revision 2.2 by completely free. We don't require any payment, subscription, or registration to access this PDF file. For 3 books every day.

How can I read PCI Local Bus Specification, Revision 2.2 on my mobile device?

After downloading PCI Local Bus Specification, Revision 2.2 PDF, you can open it with any PDF reader app on your phone or tablet. We recommend using Adobe Acrobat Reader, Apple Books, or Google Play Books for the best reading experience.

Is this the full version of PCI Local Bus Specification, Revision 2.2?

Yes, this is the complete PDF version of PCI Local Bus Specification, Revision 2.2 by Unknow. You will be able to read the entire content as in the printed version without missing any pages.

Is it legal to download PCI Local Bus Specification, Revision 2.2 PDF for free?

https://PDFdrive.to provides links to free educational resources available online. We do not store any files on our servers. Please be aware of copyright laws in your country before downloading.

The materials shared are intended for research, educational, and personal use in accordance with fair use principles.

Upgrade Premium
Most books are stored in the elastic cloud where traffic is expensive. For this reason, we have a limit on daily download.
We use cookies

We use cookies to ensure you get the best browsing experience on our website. By clicking "Accept Cookies", you agree that we can store cookies on your device in accordance with our Terms and Privacy.