Oversampling A/D Converters with Improved Signal Transfer Functions

207 Pages·2011·10.86 MB·English

by  Bupesh Pandita (auth.)

Oversampling A/D Converters with Improved
Signal Transfer Functions
ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES
Consulting Editor: Mohammed Ismail. Ohio State University
Forfurther volumes:
http://www.springer.com/series/7381
Bupesh Pandita
Oversampling A/D
Converters with Improved
Signal Transfer Functions
BupeshPandita
AMD
Markham,ON,Canada
[email protected]
ISBN978-1-4614-0274-9 e-ISBN978-1-4614-0275-6
DOI10.1007/978-1-4614-0275-6
SpringerNewYorkDordrechtHeidelbergLondon
LibraryofCongressControlNumber:2011934486
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Abstract
This book proposes a low-IF receiver architecture suitable for the realization of
single-chip receivers. To alleviate the image-rejection requirements of the front-
endfiltersanoversamplingcomplexdiscrete-timeDSADCwithasignal-transfer
function that achieves a significant filtering of interfering signals is proposed.
AfilteringADCreducesthecomplexityofthereceiverbyminimizingtherequire-
ments of analog filters in the IF digitization path. Discrete-time DS ADCs have
preciseresonantfrequencyandclockfrequencyratiosand,hence,donotrequirethe
calibrationortuningthatisnecessaryinthecaseofcontinuous-timeDSmodulator
implementations.Thisfeaturemakestheproposeddiscrete-timeDSADCidealfor
multistandardreceiverapplications.
The DS modulator signal-transfer function (STF) and noise-transfer function
(NTF) have been designed using complex filter routines based on classical filter
design procedures. With a filtering STF and stop band attenuation greater than
30 dB, the DS modulator reduces intermodulation of the desired signal and
the interfering signals at the input of the quantizer, and also avoids feedback of
thehigh-frequencyinterferingsignalsattheinputofthemodulator.
The reported complex DS ADC is intended for DTV receiver applications.
With a maximum intended sampling frequency of 128 MHz and an OSR of 16,
the ADC has been designed to support a maximum DTV signal bandwidth of
8 MHz. Except for a somewhat reduced maximum sampling frequency, the test
results of the prototype complex DS modulator are very close to the simulated
results. The IC achieved 70.9 dB SNDR over a 6 MHz band centered around
3MHz.Theimagerejectionratio(IRR)oftheDSADCwasmeasuredtobegreater
than65dB.ThemeasurementresultsconfirmthefilteringcharacteristicsoftheADC.
Thefabricatedchipconsumes177mWandoccupiesasiliconareaof2.15mm2.
v

Contents
1 Introduction................................................................ 1
1.1 MotivationandBackground.......................................... 1
1.2 DigitalTV(DTV)Receivers ......................................... 4
1.3 Outline ................................................................ 7
References................................................................... 8
2 ALow-IFComplexDSADC-BasedDTVReceiver .................... 11
2.1 Background ........................................................... 12
2.1.1 BandpassSignals.............................................. 12
2.1.2 ComplexSignals.............................................. 12
2.1.3 ComplexFilters............................................... 13
2.1.4 MismatchinComplexFilters................................. 14
2.1.5 RealMixingvs.ComplexMixing............................ 15
2.1.6 ComplexTransferFunctionDesign .......................... 17
2.2 ALow-IFDTVReceiverArchitecture............................... 18
2.3 The‘InterferingSignals’ProbleminWirelessReceivers............ 20
2.4 ApproachestoFilteringInterferingSignalsinDSADC
BasedReceivers....................................................... 22
2.4.1 FilteringInterferingSignalsintheDigitalDomain.......... 22
2.4.2 FilteringInterferingSignalsintheAnalogDomain.......... 22
2.4.3 FilteringInterferingSignalswithaFilteringSTF............ 23
2.5 SpecificationsforaComplexDSADCUsed
inaDTVReceiver.................................................... 28
2.5.1 MismatchandImageRejectionRequirements
oftheLow-IFComplexDSADC............................ 30
References................................................................... 32
3 AComplexDSModulatorwithanImprovedSTF..................... 35
3.1 DSModulatorTransferFunctions.................................... 35
3.2 NTF-STFDesignTrade-Off.......................................... 37
vii
viii Contents
3.3 Background ........................................................... 42
3.3.1 ThejLj NormanditsImpactontheNTFPoles............ 42
1
3.3.2 TheLossFunctionL(Z)...................................... 44
3.4 STF-NTFCo-DesignOptimizationAlgorithm
fortheDesignofRealDSModulators.............................. 46
3.5 PowerandPerformanceAnalysisoftheProposed
RealDSModulator.................................................. 49
3.5.1 PowerComparison.......................................... 52
3.5.2 SensitivitytoIntermodulationDue
toDACNon-linearity........................................ 53
3.5.3 StabilityComparison......................................... 56
3.6 TheSTF-NTFCo-DesignOptimizationAlgorithm
fortheDesignofComplexDSModulators......................... 60
3.7 PowerandPerformanceAnalysisoftheProposed
ComplexDSModulator ............................................. 68
3.7.1 DSModulatorwithUnitySTF.............................. 68
3.7.2 PowerComparison........................................... 70
3.7.3 SensitivitytoIntermodulationDue
toDACNon-linearity........................................ 72
3.7.4 ComparisonwithaDiscrete-TimeReceiver................. 73
3.7.5 ComparisonwithanSCþFeedForwardADC
withUnitySTF............................................... 79
3.8 DecimationforComplexDSModulators........................... 83
3.9 AdvantagesoftheProposedDSModulatorArchitecture........... 83
References.................................................................. 85
4 Architectural-LevelDesignoftheExperimentalDSModulator..... 87
4.1 Background .......................................................... 87
4.2 MismatchesinaComplexDSModulator........................... 89
4.2.1 AnImprovedComplexDSModulator...................... 97
4.3 TheSwitched-CapacitorArchitecture............................... 101
4.3.1 ComplexIntegrators ......................................... 101
4.3.2 DynamicRangeScaling ..................................... 101
4.3.3 MultibitQuantization........................................ 101
4.3.4 MultilevelDAC.............................................. 104
4.3.5 RealizingtheFeedins........................................ 104
4.3.6 TheCompleteFully-DifferentialSCArchitecture.......... 105
4.3.7 TheClockingScheme........................................ 107
4.4 System-levelBehavioralSimulations................................ 107
4.4.1 CapacitorSizing.............................................. 107
4.4.2 Clock-Jitter................................................... 117
4.4.3 OpampNonidealities......................................... 119
4.4.4 SwitchOn-Resistances....................................... 122
References.................................................................. 122
Contents ix
5 IntegratedCircuitImplementation...................................... 125
5.1 TheCompleteFourth-OrderSC-Modulator......................... 125
5.2 ClockGenerator...................................................... 127
5.3 SamplingSwitches................................................... 129
5.4 OperationalAmplifier .............................................. 129
5.4.1 MainStage ................................................ 129
5.4.2 BiasStage ................................................. 130
5.4.3 Gain-BoostingAmplifiers................................. 132
5.4.4 DeviceSizes............................................... 132
5.4.5 SCCMFBCircuit......................................... 133
5.5 Quantizers .......................................................... 134
5.5.1 Comparator................................................ 137
5.5.2 ResistorLadder............................................ 139
5.6 Layout............................................................... 139
5.6.1 Capacitor .................................................. 140
5.6.2 Switches................................................... 141
5.6.3 Comparators............................................... 142
5.6.4 Amplifiers ................................................. 142
5.6.5 TheResistorLadder....................................... 144
5.7 SubstrateandSupplyNoiseDecoupling........................... 145
5.8 TheIntegratedCircuit.............................................. 146
5.8.1 Pins........................................................ 146
5.9 TheTestSet-Up .................................................... 148
5.10 ThePCBDesign.................................................... 150
5.11 TestResults......................................................... 152
5.12 PerformanceSummary ............................................. 156
5.13 ExplainingtheDifferencesBetweentheMeasured
andtheSimulatedResults.......................................... 158
5.13.1 InstabilityandSNDRDegradation
withHigherFrequencies................................... 158
5.13.2 DifferenceBetweentheMeasured
andtheDesiredSTF....................................... 161
5.14 PowerDissipation................................................. 164
References.................................................................. 164
6 Conclusions................................................................ 167
6.1 Contributions ....................................................... 167
6.2 SuggestionsforFutureWork....................................... 168
6.2.1 Continuous-timeModulatorArchitectures................ 168
6.2.2 Frequency-TranslatingComplexDSModulator.......... 169
6.2.3 DemodulatorArchitectures................................ 169
AppendixA ................................................................... 171
ModulatorDesignExample................................................. 171
Index........................................................................... 185