Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications

213 Pages·2012·3.83 MB·English

by  © Surapong Pongyupinpanich

Technische Universita¨t Darmstadt
Fachgbereich Elektrotechnik und Informationstechnik
Fachgebiet Mikroelektronische Systeme
Optimal Design of Fixed-Point and
Floating-Point Arithmetic Units
for Scientific Applications
Surapong Pongyupinpanich
PhD Thesis, March 2012
Copyright©2012
InstituteofMicroelectronicSystems
TechnischeUniversita¨tDarmstadt
Merckstr.25,D-64283Darmstadt,Germany
Optimal Design of Fixed-Point and
Floating-Point Arithmetic Units
for Scientific Applications
Vom Fachbereich 18
Elektrotechnik und Informationstechnik
der Technischen Universita¨t Darmstadt
zur Erlangung des akademischen Grades eines
Doktor-Ingenieurs (Dr.-Ing.)
genehmigte Dissertation
von
M.Eng.
Surapong Pongyupinpanich
geboren am 17. Juni 1976
in Prachinburi, Thailand
Referent: Prof. Dr. Dr. h. c. mult. Manfred Glesner
Technische Universita¨t Darmstadt
Korreferent: Prof. Dr.-Ing. Michael Hu¨bner
Ruhr-Universita¨t Bochum
Tag der Einreichung: 20.04.2012
Tag der mu¨ndlichen Pru¨fung: 17.08.2012
D17
Darmsta¨dter Dissertationen 2012
4
Acknowledgment
This thesis is based on my work that I have started in March 2008 at Fachgebiet Mikroelek-
tronische Systeme, Institute fu¨r Datentechnik, Fachbereich Elektrotechnik und Informationstech-
nik,TechnischeUniversitta¨tDarmstadtasaresearchassistantwithascholarshipfromRamkamhang
University, Thailand. Therefore, I would like to thank Ramkamhang University for award-
ing me the scholarship to pursue my doctoral degree. Special thanks are due to my ad-
visor Prof. Dr. Dr. h.c. mult. Manfred Glesner for his advices, guidance and nice working
environment. The colourful working atmosphere at his research institute reflects his in-
ternationallyopenpersonality,qualityandcare,fromwhichIhavebenefited.
As my co-advisor, I express my acknowledgment to Prof. Dr.-Ing. Michael Hu¨bner
for his supports and advices. I would like to thank Prof. Dr.-Ing. habil. Dr. h.c. Andreas
Binder,Prof.Dr.-Ing.HaraldKlingbeilandProf.Dr.-Ing.HansEvekingforspendingtime
to be the committee of my oral examination. I would like to thank acknowledge As-
soc.Prof.Dr.SomsakChoomchuay(Ph.D.DIC)forhisrecommendationtopursuehigher
educationaldegreethatisusefulformyacademiccareer.
I gratefully acknowledge Dr.-Ing. Fizal Arya Samman who has spent much time with
me to discuss and share technical knowledge about improvement of floating-point arith-
metic topic. I thank Prof. Dr.-Ing. Peter Zipf for the time to discuss about my topic in the
particular area of system-level design, as well as to all anonymous reviewers of my jour-
nal and conference papers for the positive critics and suggestions. Many thanks are due
to the former staff members at Fachgebiet Mikroelektronische Systeme, Dr.-Ing Andre Gun-
toro, Dr.-Ing Massoud Momeni, Dr.-Ing Oana M. Cobianu, Dr.-Ing Heiko Hinkelmann,
Dr.-Ing.PetruBacinschi,Dr.-IngPingZhao,Dr.-IngLeandroMo¨lleraswellasthecurrent
staff members, Ramkumar Ganesan, Sebastian Pankalla, Francois Philipp, Christopher
Spies,ElvioDutraeSilvaandEnkhboldOchirsurenforthefriendshipandcooperation.
I would also like to express my appreciation to the staff members at Fachgebiet Inte-
grierte Elektronische Systeme, the head of the institute Prof. Dr.-Ing Klaus Hofmann and
his research and teaching assistant staffs, Harish Balasubramaniam, Yuan Fang, Ashok
Jaiswal,MareikiKaloumenos,JingNing,MuhammadSaif,AlexScho¨nberger,LufeiShen,
Boris Traskov and Haoyuan Ying. My acknowledgments are granted to Andres Schmidt
and Roland Brand for helping me in many things about software and hardware matters,
andtoSilviaHermannandIselonaKlenkforhelpingmeinmanyadministrativematters.
I express my obligation to all my supervised students who have made nice cooper-
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ations with me in the framework of bachelor/master/diploma thesis. Thank you very
much also to Gordon Smith for proof-reading and correcting the written-english thesis.
My stay in Darmstadt is enhanced by many friends and all member staffs at Banthai
Restaurant. For the fruitful friendships, I appreciate all my colleagues from Thailand,
GermanyandfromallothercountriesthatIcouldnotmentiontheminthispage.
I deeply acknowledged all my teachers in my primary school, secondary school and
my high school in Prachinburi, Nonthaburi, as well as my lecturers at King Mongkut’s
Institute of Technology Ladkrabang in Bangkok for providing me with basic and advanced
knowledge. Many thanks are also given to all teaching, technical and administrative
staff members at Ramkamhang University in Bangkok for their helps and administrative
supports.
From the depth of my heart, I am grateful to my lovely mother and my lovely father
for their patience to advice and educate me. Their love, care, dedication and their long
life educational supports connot be expressed with words. I pray for them to be blessed,
andtheirprayerisastrongmotivationformetomakethemproud. Iwouldliketothank
my younger sister Narumol Pongyupinpanich and her husband as well as my friend,
MongkolJalerntam,SakkarnKaewket,ThawatchaiWachiradusitandRachotKeatbunjon
for their supports and for taking care well my lovely parent during I am staying in Ger-
many.
Darmstadt,August2012
SurapongPongyupinpanich
Abstract
The challenge in designing a floating-point arithmetic co-processor/processor for scien-
tific and engineering applications is to improve the performance, efficiency, and compu-
tational accuracy of the arithmetic unit. The arithmetic unit should efficiently support
several mathematical functions corresponding to scientific and engineering computation
demands. Moreover, the computations should be performed as fast as possible with a
high degree of accuracy. Thus, this thesis proposes algorithm, design, architecture, and
analysis of floating-point arithmetic units particularly for scientific and engineering ap-
plicationswhichcanbeimplementedinVLSI.
Generally,performanceimprovementsandtimeefficiencywithhardwarecanbecon-
sidered from the output rate and the computational latency which is the number of gen-
erated outputs per second (output/sec) and the computational times. The output rate
can be increased by clock rate whereas the design and architecture of the hardware can
improvethecomputationaltime,whichismostlyfocusedonengineeringpractice. Obvi-
ously, in order to achieve the highest performance, the design will be based on pipeline
architecture. Nevertheless, for any hardware arithmetic unit, not only the performance
and time efficiency have to be examined, but also the computational accuracy and sta-
bility of the computational results have to be taken into account. Therefore, the floating-
point arithmetic units introduced in this dissertation will be considered in their design
and architecture based on pipeline, and an analysis of the hardware trade-off between
the VLSI areas of complexity and computational latency. Meanwhile, the floating-point
data representation is employed to improve and stabilize the computational result and
accuracyofthearithmeticunitatruntime.
The arithmetic units from a hardware point of view can be classified into two groups
dependingonhardware-basedalgorithms,i.e. thebasicarithmeticunitandtheadvanced
arithmeticunit. Thebasicarithmeticunitconsistsoftwotypesofoperationscorrespond-
ing to the number of input operands, i.e. standard operations and non-standard opera-
tions. The standard operations are addition/subtraction and multiplication operations
and the non-standard operations are product-of-sum and sum-of-product operations.
Theadvancedarithmeticunitisfrequentlyemployedinscientificandengineeringappli-
cations as elementary functions such as sine, cosine, hyperbolic sine, hyperbolic cosine,
etc. The two classes of arithmetic units can be derived in hardware-based algorithmic
formwhichisrelativelyeasyforVLSI implementationandforanalysis.
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Thebinary-treeandpartiallinearmethodsareintroducedtotheleading-one-detection
(LOD) and the integer multiplier in order to improve the performance of the floating-
point standard and non-standard operators. The investigation and synthesis results that
are based on the pipeline architecture show that both the proposed floating-point stan-
dardandnonstandardhardware-basedalgorithmscanbesimplifiedforVLSIimplemen-
tation. Meanwhile, with the proposed LOD and the proposed integer multiplier, the
floating-point standard and non-standard operators provide both high performance and
timeefficiency.
The advanced arithmetic functions are performed by the CORDIC algorithm, where
the challenges of the CORDIC algorithm are to reduce computational latency and to im-
prove computational accuracy. Therefore, two CORDIC methods, namely the double-
rotation and triple-rotation, are proposed. Their performance, efficiency, and computa-
tional accuracy are measured, analysed, and compared with conventional CORDIC re-
sults using the Matlab/Simulink tools. The proposed CORDIC methods provide better
performance,timeefficiency,andcomputationalaccuracythantheconventionalmethod,
whileatthesameprovidederrorconstraintswithfewiterations. Similarly,withthesame
numberofiterations,theproposedCORDICmethodspresentbettercomputationalaccu-
racythantheconventionalmethod. Theunifiedmicro-rotationsoftheproposedCORDIC
methods are established and analysed in order to study the performance and efficiency
basedonseveralpipelinestages.
A high precision CORDIC algorithm, based on a unified micro-rotation of the pro-
posedCORDICmethods,isintroducedwherethedouble-rotationandtriple-rotationare
applied for the normal-accuracy and high-accuracy mode, respectively. The high preci-
sion CORDIC core based on fixed-point representation is designed, implemented, and
analysed. The synchronization between the floating-point standard unit, non-standard
unit and the fixed-point elementary functional unit is demonstrated by floating-point
arithmetic accelerator architecture and also by floating-point streaming processor archi-
tecture. TheFloating-to-FixedandFixed-to-Floatingalgorithmsareintroducedfordatacon-
versionfromfloating-pointtofixed-pointrepresentationandfromfixed-pointtofloating-
pointrepresentation.
Finally, the beam phase and magnitude detector that is employed in the closed-loop
control system for heavy ion synchrotron application is used for verification of the pro-
posed CORDIC methods. In the heavy ion synchrotron application, acceleration pro-
cesses lead to beam signals with decreasing time periods for the pulses. Different modes
of oscillation are possible. However, the current system deals with the simplest mode
of oscillation, which is almost permanently presented, if no countermeasures are taken.
The beam phase control system introduced here is dedicated to cases where all bunches
are oscillating in phase. Therefore, the beam phase and magnitude detector is required
to observe the beam oscillation for the closed-loop control system. The design of the
digital phase and magnitude detector is modelled and simulated by VHDL on Model-
Sim. The simulation results based on the two patterns, ”Gap voltage” and ”Beam posi-
tion”generatedandcapturedfromthemathematicmodelandtheactualionsynchrotron
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system, SIS18 at GSI Helmholtzzentrum Schwerionenforschung, are compared with the
Matlab/SimulinksidealresultsinordertoverifytheproposedCORDICscomputation.